; ; Bret SROM V2.05 ; ; Stream 0 - Power up ; srom_0.decoded: file format binary Disassembly of section .data: 0000000000000000 <.data>: 0: 0f 01 ff 77 hw_mtpr zero,0x10f ; ICM 4: 56 01 ff 77 hw_mtpr zero,0x156 ; PALtemp22 8: 57 01 ff 77 hw_mtpr zero,0x157 ; PALtemp23 c: 39 00 40 d3 bsr ra,0xf4 ; DF - init CPU 10: 47 00 40 d3 bsr ra,0x130 ; DE/CE - init PCI 14: 2e 01 40 d3 bsr ra,0x4d0 ; DD - determine clock speed 18: 56 01 21 64 hw_mfpr t0,0x156 ; PALtemp22 1c: 20 17 04 48 sll v0,0x20,v0 20: 00 14 10 44 or v0,0x80,v0 24: 01 04 01 44 or v0,t0,t0 28: 56 01 21 74 hw_mtpr t0,0x156 ; PALtemp22 2c: 0d 0a 7f 22 lda a3,2573 30: 0d 0a 73 26 ldah a3,2573(a3) ; '\r\n\r\n' 34: 06 07 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 38: 00 00 7f 22 lda a3,0 3c: 33 17 64 4a sll a3,0x20,a3 40: 42 72 73 22 lda a3,29250(a3) 44: 65 74 73 26 ldah a3,29797(a3) ; 'Bret' 48: 01 07 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 4c: 00 07 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 50: 4f 4d 7f 22 lda a3,19791 54: 20 00 73 26 ldah a3,32(a3) 58: 33 17 64 4a sll a3,0x20,a3 5c: 20 53 73 22 lda a3,21280(a3) 60: 52 00 73 26 ldah a3,82(a3) ; ' SROM ' (with a NUL byte between R and O) 64: fa 06 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 68: 56 00 7f 22 lda a3,86 ; 'V' 6c: f8 06 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 70: 0d 0a 7f 22 lda a3,2573 74: 33 17 64 4a sll a3,0x20,a3 78: 32 2e 73 22 lda a3,11826(a3) 7c: 30 35 73 26 ldah a3,13616(a3) ; '2.05\r\n' 80: f3 06 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 84: 56 01 31 66 hw_mfpr a1,0x156 ; PALtemp22 88: 91 16 24 4a srl a1,0x20,a1 8c: e4 06 a0 d3 bsr gp,0x1c20 ; print_hex_longword(a1) 90: 0d 0a 7f 22 lda a3,2573 94: 33 17 64 4a sll a3,0x20,a3 98: 20 4d 73 22 lda a3,19744(a3) 9c: 48 7a 73 26 ldah a3,31304(a3) ; ' MHz\r\n' a0: eb 06 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) a4: 72 75 7f 22 lda a3,30066 a8: 70 20 73 26 ldah a3,8304(a3) ac: 33 17 64 4a sll a3,0x20,a3 b0: 50 6f 73 22 lda a3,28496(a3) b4: 77 65 73 26 ldah a3,25975(a3) ; 'Powerup ' b8: e5 06 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) bc: 0d 0a 7f 22 lda a3,2573 ; '\r\n' c0: e3 06 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) c4: 63 03 40 d3 bsr ra,0xe54 ; DB - Init. and testing PCI bus and data path c8: 0e 01 40 d3 bsr ra,0x504 cc: d7 01 40 d3 bsr ra,0x82c d0: ca 02 40 d3 bsr ra,0xbfc d4: 95 00 40 d3 bsr ra,0x32c d8: 82 03 40 d3 bsr ra,0xee4 dc: 14 00 40 d3 bsr ra,0x130 e0: 4f 00 40 d3 bsr ra,0x220 e4: cd 00 3f 23 lda t11,205 ; 0xcd e8: ac 05 a0 d3 bsr gp,0x179c ; diag_leds(t11) ec: 69 00 40 d3 bsr ra,0x294 f0: 00 80 ff 7b hw_rei ; DF - init CPU f4: 08 00 5f 20 lda t1,8 f8: 16 02 42 74 hw_mtpr t1,0x216 ; DC_MODE fc: df 00 3f 23 lda t11,223 ; 0xdf 100: a6 05 a0 d3 bsr gp,0x179c ; diag_leds(t11) 104: 02 00 5f 20 lda t1,2 108: 22 17 44 48 sll t1,0x20,t1 10c: 00 4e 42 24 ldah t1,19968(t1) 110: 18 01 42 74 hw_mtpr t1,0x118 ; ICSR 114: 00 00 5f 20 lda t1,0 118: 17 02 42 74 hw_mtpr t1,0x217 ; MAF_MODE 11c: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 120: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 124: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 128: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 12c: 01 80 fa 6b ret ; DE/CE - init PCI 130: ef 00 c0 d3 bsr sp,0x4f0 ; load_s4_s5() 134: 56 01 00 64 hw_mfpr v0,0x156 ; PALtemp22 138: c1 30 00 48 extbl v0,0x1,t0 13c: 01 90 20 44 and t0,0x4,t0 140: 99 d4 3b 44 cmoveq t0,0xde,t11 144: d9 d4 39 44 cmovne t0,0xce,t11 148: 01 94 e0 47 mov 0x4,t0 14c: 61 31 20 48 insbl t0,0x1,t0 150: 00 04 01 44 or v0,t0,v0 154: 56 01 00 74 hw_mtpr v0,0x156 ; PALtemp22 158: 90 05 a0 d3 bsr gp,0x179c ; diag_leds(t11) 15c: f9 00 3f 23 lda t11,249 ; 0xf9 - reg read/write miscompare ; clear PCI window base registers 160: 16 04 ff 47 clr t8 164: 76 08 bf 22 lda a5,2166 168: 35 97 a3 4a sll a5,0x1c,a5 16c: 00 04 b5 22 lda a5,1024(a5) ; 87.60000400 170: 00 94 e0 47 mov 0x4,v0 174: 51 06 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 178: 00 01 b5 22 lda a5,256(a5) 17c: ff ff 00 20 lda v0,-1(v0) 180: fc ff 1f fc bgt v0,0x174 184: 00 20 ae 22 lda a5,8192(s5) ; 87.40002000 188: 4c 06 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 18c: 40 04 ae 22 lda a5,1088(s5) ; 87.40000440 190: 4a 06 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 194: c0 00 ae 22 lda a5,192(s5) ; 87.400000C0 198: 00 ff df 22 lda t8,-256 19c: 01 00 d6 26 ldah t8,1(t8) ; FF00 1a0: 46 06 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 1a4: f3 e0 df 22 lda t8,-7949 1a8: 05 a1 d6 26 ldah t8,-24315(t8) 1ac: 36 f6 c1 4a zapnot t8,0xf,t8 ; A104E0F3 1b0: 00 01 ae 22 lda a5,256(s5) ; 87.40000100 1b4: 41 06 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 1b8: 00 06 ae 22 lda a5,1536(s5) ; 87.40000600 1bc: 08 00 df 22 lda t8,8 1c0: 00 80 f5 6e hw_ldl/p t9,0(a5) 1c4: 17 f0 e0 46 and t9,0x7,t9 1c8: 01 00 e0 e6 beq t9,0x1d0 1cc: 3b 06 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 1d0: 78 08 bf 22 lda a5,2168 1d4: 35 97 a3 4a sll a5,0x1c,a5 1d8: 00 01 b5 22 lda a5,256(a5) 1dc: ff ff df 22 lda t8,-1 1e0: 16 16 de 4a zap t8,0xf0,t8 1e4: 35 06 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 1e8: 14 07 60 d3 bsr t12,0x1e3c ; Intel PCEB configuration on PCI bus 1ec: 31 07 60 d3 bsr t12,0x1eb4 ; System EISA I/O ports config 1f0: 40 42 1f 22 lda a0,16960 1f4: 0f 00 10 26 ldah a0,15(a0) ; 1,000,000 (decimal) 1f8: 4f 06 c0 d3 bsr sp,0x1b38 ; wait(a0) 1fc: 01 80 fa 6b ret 200: 57 01 00 64 hw_mfpr v0,0x157 ; PALtemp23 204: 00 f0 00 44 and v0,0x7,v0 208: 04 00 00 e4 beq v0,0x21c 20c: 20 35 00 40 subq v0,0x1,v0 210: 19 34 e0 47 mov 0x1,t11 214: 20 07 20 4b sll t11,v0,v0 218: 20 97 02 48 sll v0,0x14,v0 21c: 01 80 fe 6b ret zero,(sp),0x1 220: 32 2e 1f 22 lda a0,11826 224: 30 35 10 26 ldah a0,13616(a0) 228: 30 17 01 4a sll a0,0x8,a0 22c: 56 00 10 22 lda a0,86(a0) 230: 56 01 31 66 hw_mfpr a1,0x156 ; PALtemp22 234: d1 94 20 4a extll a1,0x4,a1 238: 0f 00 df 22 lda t8,15 23c: 00 00 ff 22 lda t9,0 240: ab 00 c0 d3 bsr sp,0x4f0 ; load_s4_s5() 244: 00 40 2e 27 ldah t11,16384(s5) 248: 00 02 39 23 lda t11,512(t11) 24c: 00 80 39 6f hw_ldl/p t11,0(t11) 250: 93 76 21 4b srl t11,0xb,a3 254: 12 08 52 46 xor a2,a2,a2 258: e9 ff df d3 bsr sp,0x200 25c: 93 96 02 48 srl v0,0x14,a3 260: 00 1c ff 21 lda fp,7168 ; 0x1c00 264: 60 90 0f 7d hw_stq/p t7,96(fp) 268: 68 90 2f 7d hw_stq/p s0,104(fp) 26c: 78 90 4f 7d hw_stq/p s1,120(fp) 270: 80 90 6f 7d hw_stq/p s2,128(fp) 274: 70 90 8f 7d hw_stq/p s3,112(fp) 278: 00 90 0f 7e hw_stq/p a0,0(fp) 27c: 18 90 2f 7e hw_stq/p a1,24(fp) 280: 28 90 4f 7e hw_stq/p a2,40(fp) 284: 20 90 6f 7e hw_stq/p a3,32(fp) 288: 08 90 cf 7e hw_stq/p t8,8(fp) 28c: 10 90 ef 7e hw_stq/p t9,16(fp) 290: 01 80 fa 6b ret 294: 96 00 c0 d3 bsr sp,0x4f0 ; load_s4_s5() 298: 05 01 ff 77 hw_mtpr zero,0x105 ; ITB_IA 29c: 0a 02 ff 77 hw_mtpr zero,0x20a ; DTB_IA 2a0: 01 02 ff 77 hw_mtpr zero,0x201 ; DTB_CM 2a4: 00 02 ff 77 hw_mtpr zero,0x200 ; DTB_ASN 2a8: 03 01 ff 77 hw_mtpr zero,0x103 ; ITB_ASN 2ac: 09 01 ff 77 hw_mtpr zero,0x109 ; ASTRR 2b0: 0a 01 ff 77 hw_mtpr zero,0x10a ; ASTER 2b4: 08 01 ff 77 hw_mtpr zero,0x108 ; SIRR 2b8: 0c 01 ff 77 hw_mtpr zero,0x10c ; EXC_SUM 2bc: 06 02 ff 67 hw_mfpr zero,0x206 ; VA 2c0: 00 38 5f 20 lda t1,14336 2c4: 1a 01 42 74 hw_mtpr t1,0x11a ; ICPERR_STAT 2c8: 03 00 5f 20 lda t1,3 2cc: 12 02 42 74 hw_mtpr t1,0x212 ; DC_PERR_STAT 2d0: 00 40 ff 63 mb 2d4: e8 90 0d 6c hw_ldq/p v0,232(s4) ; SC_STAT IPR - clear errors 2d8: 68 91 0d 6c hw_ldq/p v0,360(s4) ; EI_STAT IPR - clear errors 2dc: 0e 01 21 64 hw_mfpr t0,0x10e ; PAL_BASE 2e0: 00 34 20 44 or t0,0x1,v0 ; set PALmode bit 2e4: 0b 01 00 74 hw_mtpr v0,0x10b ; EXC_ADDR - jump to PAL_BASE on hw_rei 2e8: 00 40 ff 63 mb 2ec: 00 40 ff 63 mb 2f0: 56 01 31 66 hw_mfpr a1,0x156 ; PALtemp22 2f4: d1 94 20 4a extll a1,0x4,a1 2f8: 40 42 1f 22 lda a0,16960 2fc: 0f 00 10 26 ldah a0,15(a0) 300: ad 05 c0 d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 304: 12 04 00 44 mov v0,a2 308: cb de 7f 26 ldah a3,-8501 30c: 33 f6 61 4a zapnot a3,0xf,a3 310: 14 34 e0 47 mov 0x1,a4 314: 00 1c bf 22 lda a5,7168 318: 70 90 95 6d hw_ldq/p s3,112(a5) 31c: 31 97 82 49 sll s3,0x14,a1 320: 68 90 35 6c hw_ldq/p t0,104(a5) 324: 60 90 55 6c hw_ldq/p t1,96(a5) 328: 01 80 fa 6b ret 32c: d0 00 3f 23 lda t11,208 ; 0xd0 330: 1a 05 a0 d3 bsr gp,0x179c ; diag_leds(t11) 334: 00 00 1f 22 lda a0,0 338: 31 37 82 49 sll s3,0x11,a1 33c: 12 04 ff 47 clr a2 340: 16 04 ff 47 clr t8 344: ca 05 c0 d3 bsr sp,0x1a70 348: ad ff df d3 bsr sp,0x200 34c: 91 76 00 48 srl v0,0x3,a1 350: c7 05 c0 d3 bsr sp,0x1a70 354: e9 01 c0 d3 bsr sp,0xafc 358: 01 80 fa 6b ret ; Initialise Dallas RTC and determine processor speed. ; v0 <- processor clock period in ps. 35c: f0 49 1f 22 lda a0,18928 360: 02 00 10 26 ldah a0,2(a0) ; 150,000 (decimal) 364: f4 05 c0 d3 bsr sp,0x1b38 ; wait(a0) 368: 0c 00 3f 22 lda a1,12 ; Dallas Reg. C 36c: 70 00 1f 22 lda a0,112 370: 80 06 a0 d3 bsr gp,0x1d74 ; pci_io_write_byte(a0, a1) 374: 71 00 1f 22 lda a0,113 ; clear interrupt flags by reading reg. C 378: 6e 06 a0 d3 bsr gp,0x1d34 ; v0 = pci_io_read_byte(a0) 37c: 0a 00 3f 22 lda a1,10 ; Dallas Reg. A 380: 70 00 1f 22 lda a0,112 384: 7b 06 a0 d3 bsr gp,0x1d74 ; pci_io_write_byte(a0, a1) 388: 26 00 3f 22 lda a1,38 ; 0x26 - turn on at 1024 Hz 38c: 71 00 1f 22 lda a0,113 390: 78 06 a0 d3 bsr gp,0x1d74 ; pci_io_write_byte(a0, a1) 394: 0b 00 3f 22 lda a1,11 ; Dallas Reg. B 398: 70 00 1f 22 lda a0,112 39c: 75 06 a0 d3 bsr gp,0x1d74 ; pci_io_write_byte(a0, a1) 3a0: 46 00 3f 22 lda a1,70 ; 0x46 - PIE, bin, 24hr 3a4: 71 00 1f 22 lda a0,113 3a8: 72 06 a0 d3 bsr gp,0x1d74 ; pci_io_write_byte(a0, a1) 3ac: 03 14 e8 47 mov 0x40,t2 3b0: 23 35 60 40 subq t2,0x1,t2 3b4: 0a 00 3f 22 lda a1,10 3b8: 70 00 1f 22 lda a0,112 3bc: 6d 06 a0 d3 bsr gp,0x1d74 ; pci_io_write_byte(a0, a1) 3c0: 71 00 1f 22 lda a0,113 3c4: 5b 06 a0 d3 bsr gp,0x1d34 ; v0 = pci_io_read_byte(a0) 3c8: 00 f0 0f 44 and v0,0x7f,v0 3cc: a0 d5 04 40 cmpeq v0,0x26,v0 3d0: 05 00 00 f4 bne v0,0x3e8 3d4: f6 ff 7f fc bgt t2,0x3b0 3d8: e9 00 3f 23 lda t11,233 ; 0xe9 3dc: ef 04 a0 d3 bsr gp,0x179c ; diag_leds(t11) 3e0: af 0e 1f 20 lda v0,3759 3e4: 01 80 fb 6b ret zero,(t12),0x1 ; Get processor speed from RTC. ; v0 <- processor clock period in ps. 3e8: 02 14 e8 47 mov 0x40,t1 3ec: 04 04 ff 47 clr t3 3f0: 05 04 ff 47 clr t4 3f4: 0c 00 3f 22 lda a1,12 ; Dallas Reg. C 3f8: 70 00 1f 22 lda a0,112 3fc: 5d 06 a0 d3 bsr gp,0x1d74 ; pci_io_write_byte(a0, a1) 400: 71 00 1f 22 lda a0,113 ; read reg. C 404: 4b 06 a0 d3 bsr gp,0x1d34 ; v0 = pci_io_read_byte(a0) 408: 10 10 08 44 and v0,0x40,a0 ; test PF - the Periodic Interrupt Flag 40c: f9 ff 1f e6 beq a0,0x3f4 410: 22 35 40 40 subq t1,0x1,t1 414: a3 19 44 40 cmplt t1,0x20,t2 418: 04 00 60 f4 bne t2,0x42c ; t1 < 32 41c: 01 00 1f 22 lda a0,1 420: 30 17 04 4a sll a0,0x20,a0 ; CC_ENA=1, COUNT=0 424: 0e 02 10 76 hw_mtpr a0,0x20e ; CC_CTL - enable cycle counter and reset to 0 428: f2 ff ff c3 br 0x3f4 42c: 00 c0 3f 62 rpcc a1 430: 31 f6 21 4a zapnot a1,0xf,a1 ; a1 = RPCC per n/1024 s, n = 1..32 434: a3 03 25 42 cmpult a1,t4,t2 438: 04 04 64 40 addq t2,t3,t3 ; inc t3 per 32-bit wraparound of RPCC 43c: 05 04 31 46 mov a1,t4 440: ec ff 5f fc bgt t1,0x3f4 444: 24 17 84 48 sll t3,0x20,t3 448: 11 04 91 40 addq t3,a1,a1 ; a1 = num proc cycles per 32/1024 s 44c: 44 29 1f 22 lda a0,10564 450: 35 3a 10 26 ldah a0,14901(a0) 454: 10 14 04 4e mulq a0,0x20,a0 ; 31,250,000,000 458: 57 05 c0 d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 45c: 01 80 fb 6b ret zero,(t12),0x1 ; Get processor speed from the SROM diagnostic port via SL_RCV. ; This subroutine expects the 'U' character (0x55) and times it using RPCC. ; Apparently unused in this SROM image, it is meant for the no-init mini-console. ; v0 <- processor clock period in ps. 460: 01 00 5f 20 lda t1,1 464: 22 37 44 48 sll t1,0x21,t1 468: 15 01 42 74 hw_mtpr t1,0x115 ; HWINT_CLR 46c: 01 00 3f 20 lda t0,1 470: 01 00 3f 20 lda t0,1 474: 21 17 24 48 sll t0,0x20,t0 478: 08 00 df 22 lda t8,8 47c: 17 01 f7 66 hw_mfpr t9,0x117 ; SL_RCV 480: fe ff ff f6 bne t9,0x47c 484: 0e 02 21 74 hw_mtpr t0,0x20e ; CC_CTL 488: 17 01 f7 66 hw_mfpr t9,0x117 ; SL_RCV 48c: fe ff ff e6 beq t9,0x488 490: 36 35 c0 42 subq t8,0x1,t8 494: 04 00 c0 e6 beq t8,0x4a8 498: 17 01 f7 66 hw_mfpr t9,0x117 ; SL_RCV 49c: fe ff ff f6 bne t9,0x498 4a0: 36 35 c0 42 subq t8,0x1,t8 4a4: f8 ff df f6 bne t8,0x488 4a8: 00 c0 1f 63 rpcc t10 4ac: 38 f6 01 4b zapnot t10,0xf,t10 4b0: 80 76 00 4b srl t10,0x3,v0 4b4: 31 f6 01 48 zapnot v0,0xf,a1 ; a1 = proc. clock cycles per one bit of 'U' 4b8: 34 00 1f 22 lda a0,52 4bc: 40 42 1f 20 lda v0,16960 4c0: 0f 00 00 24 ldah v0,15(v0) 4c4: 10 04 10 4c mulq v0,a0,a0 ; a0 = 52,000,000 - approx. 1 bit in ps at 19200 baud 4c8: 3b 05 c0 d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 4cc: 01 80 fb 6b ret zero,(t12),0x1 ; DD - determine clock speed 4d0: dd 00 3f 23 lda t11,221 ; 0xdd 4d4: b1 04 a0 d3 bsr gp,0x179c ; diag_leds(t11) 4d8: a0 ff 7f d3 bsr t12,0x35c ; v0 = clock period in ps, ref. from RTC. 4dc: 11 04 00 44 mov v0,a1 4e0: 40 42 1f 22 lda a0,16960 4e4: 0f 00 10 26 ldah a0,15(a0) 4e8: 33 05 c0 d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 4ec: 01 80 fa 6b ret ; load_s4_s5() ; Load constants into s4 and s5: ; s4 <- FF.FFF00000 ; 21164 CPU IPR region ; s5 <- 87.40000000 ; 21172-CA CIA Main CSRs base address 4f0: f0 ff 1f 24 ldah v0,-16 4f4: 0d 16 1c 48 zap v0,0xe0,s4 ; s4 <- FF.FFF00000 4f8: 74 08 1f 20 lda v0,2164 ; 0x874 4fc: 2e 97 03 48 sll v0,0x1c,s5 ; s5 <- 87.40000000 500: 01 80 fe 6b ret zero,(sp),0x1 ; DC - Sizing and initializing the Scache 504: dc 00 3f 23 lda t11,220 ; 0xdc 508: a4 04 a0 d3 bsr gp,0x179c ; diag_leds(t11) 50c: 00 e0 7f 20 lda t2,-8192 510: 01 00 63 24 ldah t2,1(t2) 514: a8 90 4d 6c hw_ldq/p t1,168(s4) ; SC_CTL IPR - Scache control 518: 02 00 43 44 and t1,t2,t1 51c: 02 00 40 f4 bne t1,0x528 520: ff 00 3f 23 lda t11,255 ; 0xff 524: 9d 04 a0 d3 bsr gp,0x179c ; diag_leds(t11) 528: 80 b6 41 48 srl t1,0xd,v0 52c: a3 f3 00 40 cmpult v0,0x7,t2 530: 04 00 60 e4 beq t2,0x544 534: 01 00 60 44 and t2,v0,t0 538: 23 37 60 48 sll t2,0x1,t2 53c: fd ff 3f e4 beq t0,0x534 540: 22 b7 21 48 sll t0,0xd,t1 544: 02 10 3f 20 lda t0,4098 548: 03 04 41 44 or t1,t0,t2 54c: 00 40 ff 63 mb 550: a8 90 6d 7c hw_stq/p t2,168(s4) ; SC_CTL IPR - Scache control 554: 00 40 ff 63 mb 558: da 00 3f 23 lda t11,218 ; 0xda 55c: 8f 04 a0 d3 bsr gp,0x179c ; diag_leds(t11) 560: 40 80 3f 21 lda s0,-32704 564: 01 00 29 25 ldah s0,1(s0) ; s0 = 0x8040: disable Bcache, set EI_ECC and EI_DIS_ERR 568: 00 40 ff 63 mb 56c: 28 91 2d 7d hw_stq/p s0,296(s4) ; BC_CONTROL IPR - Bcache interface 570: 00 40 ff 63 mb 574: 08 04 ff 47 clr t7 578: 00 40 ee 25 ldah fp,16384(s5) 57c: 00 02 af 22 lda a5,512(fp) ; a5 = 87.8000.0200 - GRU CACHE_CNFG 580: 00 80 b5 6c hw_ldl/p t4,0(a5) 584: 12 04 a5 44 mov t4,a2 588: 65 43 7f 22 lda a3,17253 58c: 66 67 73 26 ldah a3,26470(a3) 590: 33 17 64 4a sll a3,0x20,a3 594: 43 61 73 22 lda a3,24899(a3) 598: 63 68 73 26 ldah a3,26723(a3) ; 'CacheCfg' 59c: df 05 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 5a0: 01 00 9f 21 lda s3,1 5a4: 01 20 8c 25 ldah s3,8193(s3) 5a8: 56 01 31 66 hw_mfpr a1,0x156 ; PALtemp22 5ac: d1 94 20 4a extll a1,0x4,a1 5b0: 40 42 1f 22 lda a0,16960 5b4: 0f 00 10 26 ldah a0,15(a0) 5b8: ff 04 c0 d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 5bc: 40 01 00 74 hw_mtpr v0,0x140 ; PALtemp0 5c0: fa 16 1f 22 lda a0,5882 5c4: 11 04 00 44 mov v0,a1 5c8: fb 04 c0 d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 5cc: 20 37 02 48 sll v0,0x11,v0 5d0: 09 04 09 44 or v0,s0,s0 5d4: ee 00 3f 23 lda t11,238 ; 0xee 5d8: 82 b6 a1 48 srl t4,0xd,t1 5dc: 02 f0 40 44 and t1,0x7,t1 5e0: 02 00 40 f4 bne t1,0x5ec 5e4: 6d 04 a0 d3 bsr gp,0x179c ; diag_leds(t11) 5e8: 56 00 e0 c3 br 0x744 5ec: 08 04 48 44 or t1,t7,t7 5f0: 82 76 a1 48 srl t4,0xb,t1 5f4: 02 70 40 44 and t1,0x3,t1 5f8: 56 01 00 64 hw_mfpr v0,0x156 ; PALtemp22 5fc: c4 94 00 48 extll v0,0x4,t3 600: 04 01 1f 22 lda a0,260 604: 30 05 90 40 subq t3,a0,a0 608: 21 00 3f 22 lda a1,33 60c: ea 04 c0 d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 610: 04 04 00 44 mov v0,t3 614: 06 04 ff 47 clr t5 618: 12 00 40 e4 beq t1,0x664 61c: 2f 00 40 e0 blbc t1,0x6dc 620: 82 36 40 48 srl t1,0x1,t1 624: 1e 00 40 e0 blbc t1,0x6a0 628: bb cc ff 21 lda fp,-13125 62c: de ee ef 25 ldah fp,-4386(fp) 630: 2f 17 e4 49 sll fp,0x20,fp 634: 77 88 df 23 lda sp,-30601 638: 9a aa de 27 ldah sp,-21862(sp) 63c: 3e f6 c1 4b zapnot sp,0xf,sp 640: 0f 04 fe 45 or fp,sp,fp 644: 44 00 c0 d3 bsr sp,0x758 648: 7c 7c ff 21 lda fp,31868 64c: fc fc ef 25 ldah fp,-772(fp) 650: 2f 17 e4 49 sll fp,0x20,fp 654: 0e 1e ef 21 lda fp,7694(fp) 658: 1e 3e ef 25 ldah fp,15902(fp) 65c: 3e 00 c0 d3 bsr sp,0x758 660: 2c 00 e0 c3 br 0x714 664: 99 99 ff 21 lda fp,-26215 668: 9a aa ef 25 ldah fp,-21862(fp) 66c: 2f 17 e4 49 sll fp,0x20,fp 670: 66 77 df 23 lda sp,30566 674: 88 99 de 27 ldah sp,-26232(sp) 678: 3e f6 c1 4b zapnot sp,0xf,sp 67c: 0f 04 fe 45 or fp,sp,fp 680: 35 00 c0 d3 bsr sp,0x758 684: 3c 3c ff 21 lda fp,15420 688: 3c 7c ef 25 ldah fp,31804(fp) 68c: 2f 17 e4 49 sll fp,0x20,fp 690: 0e 1e ef 21 lda fp,7694(fp) 694: 3e 3c ef 25 ldah fp,15422(fp) 698: 2f 00 c0 d3 bsr sp,0x758 69c: 1d 00 e0 c3 br 0x714 6a0: 99 aa ff 21 lda fp,-21863 6a4: ab bb ef 25 ldah fp,-17493(fp) 6a8: 2f 17 e4 49 sll fp,0x20,fp 6ac: 66 77 df 23 lda sp,30566 6b0: 88 99 de 27 ldah sp,-26232(sp) 6b4: 3e f6 c1 4b zapnot sp,0xf,sp 6b8: 0f 04 fe 45 or fp,sp,fp 6bc: 26 00 c0 d3 bsr sp,0x758 6c0: 3c 7c ff 21 lda fp,31804 6c4: 7c fc ef 25 ldah fp,-900(fp) 6c8: 2f 17 e4 49 sll fp,0x20,fp 6cc: 0e 1e ef 21 lda fp,7694(fp) 6d0: 1e 3e ef 25 ldah fp,15902(fp) 6d4: 20 00 c0 d3 bsr sp,0x758 6d8: 0e 00 e0 c3 br 0x714 6dc: 99 bb ff 21 lda fp,-17511 6e0: bc cc ef 25 ldah fp,-13124(fp) 6e4: 2f 17 e4 49 sll fp,0x20,fp 6e8: 77 88 df 23 lda sp,-30601 6ec: 89 99 de 27 ldah sp,-26231(sp) 6f0: 3e f6 c1 4b zapnot sp,0xf,sp 6f4: 0f 04 fe 45 or fp,sp,fp 6f8: 17 00 c0 d3 bsr sp,0x758 6fc: 3c 7c ff 21 lda fp,31804 700: 7c fc ef 25 ldah fp,-900(fp) 704: 2f 17 e4 49 sll fp,0x20,fp 708: 0e 1c ef 21 lda fp,7182(fp) 70c: 1e 1e ef 25 ldah fp,7710(fp) 710: 11 00 c0 d3 bsr sp,0x758 714: 11 11 ff 21 lda fp,4369 718: 11 11 ef 25 ldah fp,4369(fp) 71c: 2f 17 e4 49 sll fp,0x20,fp 720: 11 11 ef 21 lda fp,4369(fp) 724: 11 11 ef 25 ldah fp,4369(fp) 728: 0b 00 c0 d3 bsr sp,0x758 72c: 57 01 08 75 hw_mtpr t7,0x157 ; PALtemp23 730: 00 10 ee 25 ldah fp,4096(s5) 734: 00 80 8f 7d hw_stl/p s3,0(fp) 738: 00 40 ff 63 mb 73c: 2b 00 60 d3 bsr t12,0x7ec 740: 01 80 fa 6b ret 744: 00 10 ee 25 ldah fp,4096(s5) 748: 00 80 8f 7d hw_stl/p s3,0(fp) 74c: 00 40 ff 63 mb 750: 0a 00 60 d3 bsr t12,0x77c 754: 01 80 fa 6b ret 758: 04 15 bf 20 lda t4,5380 75c: 0c 00 a5 24 ldah t4,12(t4) 760: d3 00 e4 49 extbl fp,t3,a3 764: d2 00 a6 48 extbl t4,t5,a2 768: 33 07 72 4a sll a3,a2,a3 76c: 08 04 68 46 or a3,t7,t7 770: 06 34 c0 40 addq t5,0x1,t5 774: 01 80 fe 6b ret zero,(sp),0x1 778: 08 04 a0 d3 bsr gp,0x179c ; diag_leds(t11) 77c: 08 04 ff 47 clr t7 780: 00 40 ae 27 ldah gp,16384(s5) 784: 00 02 bd 23 lda gp,512(gp) 788: 00 80 bd 6f hw_ldl/p gp,0(gp) 78c: 9d 96 a0 4b srl gp,0x4,gp 790: 1d f0 a1 47 and gp,0xf,gp 794: 39 97 a0 4b sll gp,0x4,t11 798: 08 04 28 47 or t11,t7,t7 79c: 39 17 a1 4b sll gp,0x8,t11 7a0: 08 04 28 47 or t11,t7,t7 7a4: 23 1c 3f 23 lda t11,7203 7a8: 39 97 21 4b sll t11,0xc,t11 7ac: 08 04 28 47 or t11,t7,t7 7b0: 09 31 20 45 andnot s0,0x1,s0 7b4: 00 40 ff 63 mb 7b8: c8 91 0d 7d hw_stq/p t7,456(s4) 7bc: 00 40 ff 63 mb 7c0: 28 91 2d 7d hw_stq/p s0,296(s4) 7c4: 00 40 ff 63 mb 7c8: 00 06 ae 23 lda gp,1536(s5) 7cc: 00 80 bd 6f hw_ldl/p gp,0(gp) 7d0: 08 00 3f 23 lda t11,8 7d4: 19 01 b9 47 andnot gp,t11,t11 7d8: 00 06 ae 23 lda gp,1536(s5) 7dc: 00 80 3d 7f hw_stl/p t11,0(gp) 7e0: 00 40 ff 63 mb 7e4: 00 80 3d 6f hw_ldl/p t11,0(gp) 7e8: 01 80 fb 6b ret zero,(t12),0x1 7ec: 09 34 20 45 or s0,0x1,s0 7f0: 57 01 08 65 hw_mfpr t7,0x157 ; PALtemp23 7f4: 00 40 ff 63 mb 7f8: 28 91 2d 7d hw_stq/p s0,296(s4) 7fc: 00 40 ff 63 mb 800: c8 91 0d 7d hw_stq/p t7,456(s4) 804: 00 40 ff 63 mb 808: 00 06 ae 23 lda gp,1536(s5) 80c: 00 80 bd 6f hw_ldl/p gp,0(gp) 810: 08 00 3f 23 lda t11,8 814: 19 04 b9 47 or gp,t11,t11 818: 00 06 ae 23 lda gp,1536(s5) 81c: 00 80 3d 7f hw_stl/p t11,0(gp) 820: 00 40 ff 63 mb 824: 00 80 3d 6f hw_ldl/p t11,0(gp) 828: 01 80 fb 6b ret zero,(t12),0x1 ; D9 - Sizing memory 82c: 0a 04 ff 47 clr s1 830: 0b 04 ff 47 clr s2 834: d9 00 3f 23 lda t11,217 ; 0xd9 838: d8 03 a0 d3 bsr gp,0x179c ; diag_leds(t11) 83c: 00 10 ee 25 ldah fp,4096(s5) 840: 00 0b af 22 lda a5,2816(fp) 844: f6 00 3f 23 lda t11,246 ; 0xf6 848: 00 0b af 22 lda a5,2816(fp) 84c: 40 c1 df 22 lda t8,-16064 850: 39 60 d6 26 ldah t8,24633(t8) 854: 99 04 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 858: 40 0b af 22 lda a5,2880(fp) 85c: 40 c1 df 22 lda t8,-16064 860: 39 60 d6 26 ldah t8,24633(t8) 864: 95 04 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 868: 80 0b af 22 lda a5,2944(fp) 86c: 40 c1 df 22 lda t8,-16064 870: 39 60 d6 26 ldah t8,24633(t8) 874: 91 04 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 878: 00 06 0f 22 lda a0,1536(fp) 87c: 80 03 3f 22 lda a1,896 880: 16 04 ff 47 clr t8 884: 15 04 11 42 addq a0,a1,a5 888: 8c 04 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) 88c: 31 15 30 42 subq a1,0x80,a1 890: fc ff 3f fa bge a1,0x884 894: 03 14 e1 47 mov 0x8,t2 898: 06 34 e0 47 mov 0x1,t5 89c: 0a 04 ff 47 clr s1 8a0: 02 04 ff 47 clr t1 8a4: 90 36 40 48 srl t1,0x1,a0 8a8: 11 04 ff 47 clr a1 8ac: 12 14 f0 47 mov 0x80,a2 8b0: 13 14 e0 47 mov 0,a3 8b4: 14 74 e0 47 mov 0x3,a4 8b8: 55 00 80 d3 bsr at,0xa10 8bc: 30 57 63 48 sll t2,0x1a,a0 8c0: d0 02 5f 44 cmovlbc t1,zero,a0 8c4: 20 00 1f 24 ldah v0,32 8c8: 91 76 00 48 srl v0,0x3,a1 8cc: 12 04 ff 47 clr a2 8d0: 16 04 ff 47 clr t8 8d4: 66 04 c0 d3 bsr sp,0x1a70 8d8: 11 11 df 22 lda t8,4369 8dc: 11 11 d6 26 ldah t8,4369(t8) 8e0: 36 17 c4 4a sll t8,0x20,t8 8e4: 11 11 d6 22 lda t8,4369(t8) 8e8: 11 11 d6 26 ldah t8,4369(t8) ; 0x1111111111111111 8ec: 91 36 60 48 srl t2,0x1,a1 8f0: 13 04 10 46 mov a0,a3 8f4: 67 00 60 d3 bsr t12,0xa94 8f8: 37 00 20 e4 beq t0,0x9d8 8fc: 04 00 00 e7 beq t10,0x910 900: 00 14 47 40 addq t1,0x38,v0 904: 20 07 c0 48 sll t5,v0,v0 908: 0a 04 0a 44 or v0,s1,s1 90c: 32 00 e0 c3 br 0x9d8 910: 36 37 c0 4a sll t8,0x1,t8 914: 00 01 70 22 lda a3,256(a0) 918: 5e 00 60 d3 bsr t12,0xa94 91c: 03 00 20 f4 bne t0,0x92c 920: 00 14 40 40 addq t1,0,v0 924: 20 07 c0 48 sll t5,v0,v0 928: 2b 00 e0 c3 br 0x9d8 92c: 90 36 40 48 srl t1,0x1,a0 930: 11 04 ff 47 clr a1 934: 12 14 e4 47 mov 0x20,a2 938: 13 14 e0 47 mov 0,a3 93c: 14 74 e0 47 mov 0x3,a4 940: 33 00 80 d3 bsr at,0xa10 944: 30 17 63 48 sll t2,0x18,a0 948: d0 02 5f 44 cmovlbc t1,zero,a0 94c: 00 02 70 22 lda a3,512(a0) 950: 33 33 df 22 lda t8,13107 954: 33 33 d6 26 ldah t8,13107(t8) 958: 36 17 c4 4a sll t8,0x20,t8 95c: 33 33 d6 22 lda t8,13107(t8) 960: 33 33 d6 26 ldah t8,13107(t8) 964: 4b 00 60 d3 bsr t12,0xa94 968: 03 00 20 f4 bne t0,0x978 96c: 00 14 41 40 addq t1,0x8,v0 970: 20 07 c0 48 sll t5,v0,v0 974: 18 00 e0 c3 br 0x9d8 978: 90 36 40 48 srl t1,0x1,a0 97c: 11 04 ff 47 clr a1 980: 12 14 e1 47 mov 0x8,a2 984: 13 14 e0 47 mov 0,a3 988: 14 74 e0 47 mov 0x3,a4 98c: 20 00 80 d3 bsr at,0xa10 990: 30 d7 62 48 sll t2,0x16,a0 994: d0 02 5f 44 cmovlbc t1,zero,a0 998: 44 44 df 22 lda t8,17476 99c: 44 44 d6 26 ldah t8,17476(t8) 9a0: 36 17 c4 4a sll t8,0x20,t8 9a4: 44 44 d6 22 lda t8,17476(t8) 9a8: 44 44 d6 26 ldah t8,17476(t8) 9ac: 91 36 60 48 srl t2,0x1,a1 9b0: 13 04 10 46 mov a0,a3 9b4: 37 00 60 d3 bsr t12,0xa94 9b8: 07 00 20 e4 beq t0,0x9d8 9bc: 04 00 00 e7 beq t10,0x9d0 9c0: 00 14 47 40 addq t1,0x38,v0 9c4: 20 07 c0 48 sll t5,v0,v0 9c8: 0a 04 0a 44 or v0,s1,s1 9cc: 02 00 e0 c3 br 0x9d8 9d0: 00 14 42 40 addq t1,0x10,v0 9d4: 20 07 c0 48 sll t5,v0,v0 9d8: 0a 04 0a 44 or v0,s1,s1 9dc: 02 34 40 40 addq t1,0x1,t1 9e0: b0 ff 5f f0 blbs t1,0x8a4 9e4: 30 55 40 40 subq t1,0x2,a0 9e8: 22 00 c0 d3 bsr sp,0xa74 9ec: 00 80 e0 7f hw_stl/p zero,0(v0) 9f0: a0 95 40 40 cmpeq t1,0x4,v0 9f4: ab ff 1f e4 beq v0,0x8a4 9f8: 20 f6 41 49 zapnot s1,0xf,v0 9fc: 02 00 00 f4 bne v0,0xa08 a00: fa 00 3f 23 lda t11,250 ; 0xfa a04: 65 03 a0 d3 bsr gp,0x179c ; diag_leds(t11) a08: 52 00 60 d3 bsr t12,0xb54 a0c: 01 80 fa 6b ret a10: 96 16 21 4a srl a1,0x8,t8 a14: 20 97 63 4a sll a3,0x1c,v0 a18: 16 04 16 44 or v0,t8,t8 a1c: 00 04 ff 47 clr v0 a20: b7 15 50 42 cmpeq a2,0x80,t9 a24: c0 54 e0 46 cmovne t9,0x2,v0 a28: b7 15 44 42 cmpeq a2,0x20,t9 a2c: c0 34 e0 46 cmovne t9,0x1,v0 a30: 20 37 00 48 sll v0,0x1,v0 a34: 16 04 16 44 or v0,t8,t8 a38: 95 56 40 4a srl a2,0x2,a5 a3c: 35 35 a0 42 subq a5,0x1,a5 a40: 35 97 a0 4a sll a5,0x4,a5 a44: 16 04 b6 46 or a5,t8,t8 a48: 00 30 80 46 and a4,0x1,v0 a4c: 20 17 00 48 sll v0,0,v0 a50: 16 04 16 44 or v0,t8,t8 a54: 80 36 80 4a srl a4,0x1,v0 a58: 20 f7 01 48 sll v0,0xf,v0 a5c: 16 04 16 44 or v0,t8,t8 a60: 06 00 c0 d3 bsr sp,0xa7c a64: 15 04 00 44 mov v0,a5 a68: f6 00 3f 23 lda t11,246 ; 0xf6 a6c: 13 04 c0 d3 bsr sp,0x1abc ; stl_checked(t8, a5, t11) a70: 01 80 fc 6b ret zero,(at),0x1 a74: 81 36 00 4a srl a0,0x1,t0 a78: 01 00 e0 c3 br 0xa80 a7c: 01 04 10 46 mov a0,t0 a80: 21 f7 20 48 sll t0,0x7,t0 a84: 00 10 0e 24 ldah v0,4096(s5) a88: 00 06 00 20 lda v0,1536(v0) a8c: 00 04 01 40 addq v0,t0,v0 a90: 01 80 fe 6b ret zero,(sp),0x1 a94: 12 04 ff 47 clr a2 a98: 18 00 c0 d3 bsr sp,0xafc a9c: 07 04 10 46 mov a0,t6 aa0: 10 04 73 46 mov a3,a0 aa4: f2 03 c0 d3 bsr sp,0x1a70 aa8: 14 00 c0 d3 bsr sp,0xafc aac: 10 04 e7 44 mov t6,a0 ab0: 14 04 31 46 mov a1,a4 ab4: d5 12 c0 4a extwl t8,0,a5 ab8: 01 04 ff 47 clr t0 abc: 00 90 f0 6e hw_ldq/p t9,0(a0) ac0: 19 d4 e0 47 mov 0x6,t11 ac4: c0 02 f9 4a extwl t9,t11,v0 ac8: b8 05 a0 42 cmpeq a5,v0,t10 acc: 01 04 01 43 addq t10,t0,t0 ad0: 39 55 20 43 subq t11,0x2,t11 ad4: fb ff 3f fb bge t11,0xac4 ad8: 34 35 80 42 subq a4,0x1,a4 adc: 10 14 01 42 addq a0,0x8,a0 ae0: f6 ff 9f fe bgt a4,0xabc ae4: 34 57 20 4a sll a1,0x2,a4 ae8: 18 08 34 44 xor t0,a4,t10 aec: 10 04 e7 44 mov t6,a0 af0: 02 00 c0 d3 bsr sp,0xafc af4: 00 04 ff 47 clr v0 af8: 01 80 fb 6b ret zero,(t12),0x1 afc: 11 04 00 d0 bsr v0,0x1b44 ; save_regs() b00: 09 00 20 e1 blbc s0,0xb28 b04: be fd df d3 bsr sp,0x200 b08: 07 00 00 e4 beq v0,0xb28 b0c: 04 04 b5 46 mov a5,t3 b10: 05 04 d6 46 mov t8,t4 b14: 16 04 ff 47 clr t8 b18: 10 04 10 40 addq v0,a0,a0 b1c: d4 03 c0 d3 bsr sp,0x1a70 b20: 09 00 e0 c3 br 0xb48 b24: 07 04 00 d0 bsr v0,0x1b44 ; save_regs() b28: 04 04 b5 46 mov a5,t3 b2c: 05 04 d6 46 mov t8,t4 b30: 16 04 ff 47 clr t8 b34: 03 14 e1 47 mov 0x8,t2 b38: 01 00 10 26 ldah a0,1(a0) b3c: cc 03 c0 d3 bsr sp,0x1a70 b40: 23 35 60 40 subq t2,0x1,t2 b44: fc ff 7f fc bgt t2,0xb38 b48: 15 04 84 44 mov t3,a5 b4c: 16 04 a5 44 mov t4,t8 b50: 0e 04 e0 c3 br 0x1b8c ; restore_regs() b54: d8 00 3f 23 lda t11,216 ; 0xd8 b58: 10 03 a0 d3 bsr gp,0x179c ; diag_leds(t11) b5c: 00 94 e0 47 mov 0x4,v0 b60: 02 04 ff 47 clr t1 b64: 03 14 f0 47 mov 0x80,t2 b68: 05 04 60 4c mulq t2,v0,t4 b6c: 06 04 ff 47 clr t5 b70: 0c 04 ff 47 clr s3 b74: 08 00 ff 20 lda t6,8 b78: 00 70 e0 44 and t6,0x3,v0 b7c: 02 00 00 f4 bne v0,0xb88 b80: c4 00 46 49 extbl s1,t5,t3 b84: 10 04 ff 47 clr a0 b88: a0 b3 e0 40 cmpult t6,0x5,v0 b8c: 94 74 00 44 cmoveq v0,0x3,a4 b90: d4 34 00 44 cmovne v0,0x1,a4 b94: 00 70 80 44 and t3,0x3,v0 b98: a0 05 80 42 cmpeq a4,v0,v0 b9c: 0d 00 00 e4 beq v0,0xbd4 ba0: 13 14 e0 47 mov 0,a3 ba4: 11 04 5f 44 or t1,zero,a1 ba8: 12 04 7f 44 or t2,zero,a2 bac: 98 ff 9f d3 bsr at,0xa10 bb0: 20 97 a2 48 sll t4,0x14,v0 bb4: 02 04 40 40 addq t1,v0,t1 bb8: 0c 04 85 41 addq s3,t4,s3 bbc: 14 70 80 44 and t3,0x3,a4 bc0: a0 75 80 42 cmpeq a4,0x3,v0 bc4: 03 00 00 e4 beq v0,0xbd4 bc8: 20 97 a2 48 sll t4,0x14,v0 bcc: 02 04 40 40 addq t1,v0,t1 bd0: 0c 04 85 41 addq s3,t4,s3 bd4: 10 34 00 42 addq a0,0x1,a0 bd8: 84 56 80 48 srl t3,0x2,t3 bdc: 27 35 e0 40 subq t6,0x1,t6 be0: e5 ff ff f4 bne t6,0xb78 be4: 83 56 60 48 srl t2,0x2,t2 be8: 85 56 a0 48 srl t4,0x2,t4 bec: 06 34 c0 40 addq t5,0x1,t5 bf0: a0 95 c0 40 cmpeq t5,0x4,v0 bf4: df ff 1f e4 beq v0,0xb74 bf8: 01 80 fb 6b ret zero,(t12),0x1 bfc: d7 00 3f 23 lda t11,215 ; 0xd7 c00: e6 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) c04: 0f 04 ff 47 clr fp c08: 7d fd df d3 bsr sp,0x200 c0c: 06 04 00 44 mov v0,t5 c10: 00 02 ff 24 ldah t6,512 c14: 00 00 1f 22 lda a0,0 c18: 07 00 c0 e4 beq t5,0xc38 c1c: d6 00 3f 23 lda t11,214 ; 0xd6 c20: de 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) c24: 4f 00 80 d3 bsr at,0xd64 c28: 03 00 00 e7 beq t10,0xc38 c2c: f5 00 3f 23 lda t11,245 ; 0xf5 c30: d1 fe 7f d3 bsr t12,0x778 c34: 06 04 ff 47 clr t5 c38: d5 00 3f 23 lda t11,213 ; 0xd5 c3c: d7 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) c40: 0f 34 e0 47 mov 0x1,fp c44: 47 00 80 d3 bsr at,0xd64 c48: 02 00 00 e7 beq t10,0xc54 c4c: e5 00 3f 23 lda t11,229 ; 0xe5 c50: 6c 00 00 f7 bne t10,0xe04 c54: 12 34 e0 47 mov 0x1,a2 c58: 09 00 c0 e4 beq t5,0xc80 c5c: d4 00 3f 23 lda t11,212 ; 0xd4 c60: ce 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) c64: 91 76 c0 48 srl t5,0x3,a1 c68: 81 03 c0 d3 bsr sp,0x1a70 c6c: 89 03 c0 d3 bsr sp,0x1a94 c70: 03 00 00 e7 beq t10,0xc80 c74: f4 00 3f 23 lda t11,244 ; 0xf4 c78: bf fe 7f d3 bsr t12,0x778 c7c: 06 04 ff 47 clr t5 c80: d3 00 3f 23 lda t11,211 ; 0xd3 c84: c5 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) c88: e4 00 3f 23 lda t11,228 ; 0xe4 c8c: 91 76 e0 48 srl t6,0x3,a1 c90: 77 03 c0 d3 bsr sp,0x1a70 c94: 7f 03 c0 d3 bsr sp,0x1a94 c98: 5a 00 00 f7 bne t10,0xe04 c9c: 20 00 1f 20 lda v0,32 ca0: a0 09 0c 40 cmplt v0,s3,v0 ca4: 06 00 00 e4 beq v0,0xcc0 ca8: 20 97 82 49 sll s3,0x14,v0 cac: 30 05 07 40 subq v0,t6,a0 cb0: 6f 03 c0 d3 bsr sp,0x1a70 cb4: 77 03 c0 d3 bsr sp,0x1a94 cb8: 52 00 00 f7 bne t10,0xe04 cbc: 10 04 ff 47 clr a0 cc0: 55 55 df 22 lda t8,21845 cc4: 55 55 d6 26 ldah t8,21845(t8) cc8: 36 17 c4 4a sll t8,0x20,t8 ccc: 55 55 d6 22 lda t8,21845(t8) cd0: 55 55 d6 26 ldah t8,21845(t8) cd4: 12 14 e0 47 mov 0,a2 cd8: 0d 00 c0 e4 beq t5,0xd10 cdc: d2 00 3f 23 lda t11,210 ; 0xd2 ce0: ae 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) ce4: 02 54 e0 47 mov 0x2,t1 ce8: 22 35 40 40 subq t1,0x1,t1 cec: 91 76 c0 48 srl t5,0x3,a1 cf0: 5f 03 c0 d3 bsr sp,0x1a70 cf4: 67 03 c0 d3 bsr sp,0x1a94 cf8: 03 00 00 e7 beq t10,0xd08 cfc: f3 00 3f 23 lda t11,243 ; 0xf3 d00: 9d fe 7f d3 bsr t12,0x778 d04: 06 04 ff 47 clr t5 d08: 16 05 f6 47 not t8,t8 d0c: f6 ff 5f fc bgt t1,0xce8 d10: d1 00 3f 23 lda t11,209 ; 0xd1 d14: a1 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) d18: 02 54 e0 47 mov 0x2,t1 d1c: 22 35 40 40 subq t1,0x1,t1 d20: e3 00 3f 23 lda t11,227 ; 0xe3 d24: 91 76 e0 48 srl t6,0x3,a1 d28: 51 03 c0 d3 bsr sp,0x1a70 d2c: 59 03 c0 d3 bsr sp,0x1a94 d30: 34 00 00 f7 bne t10,0xe04 d34: 20 00 1f 20 lda v0,32 d38: a0 09 0c 40 cmplt v0,s3,v0 d3c: 06 00 00 e4 beq v0,0xd58 d40: 20 97 82 49 sll s3,0x14,v0 d44: 30 05 07 40 subq v0,t6,a0 d48: 49 03 c0 d3 bsr sp,0x1a70 d4c: 51 03 c0 d3 bsr sp,0x1a94 d50: 2c 00 00 f7 bne t10,0xe04 d54: 10 04 ff 47 clr a0 d58: 16 05 f6 47 not t8,t8 d5c: ef ff 5f fc bgt t1,0xd1c d60: 01 80 fa 6b ret d64: 02 04 ff 47 clr t1 d68: 11 14 e1 47 mov 0x8,a1 d6c: 12 04 ff 47 clr a2 d70: 16 14 e0 47 mov 0,t8 d74: 3e 03 c0 d3 bsr sp,0x1a70 d78: 02 00 e0 e5 beq fp,0xd84 d7c: 5f ff df d3 bsr sp,0xafc d80: 01 00 e0 c3 br 0xd88 d84: 67 ff df d3 bsr sp,0xb24 d88: 03 34 e0 47 mov 0x1,t2 d8c: 16 04 63 44 mov t2,t8 d90: 55 06 50 40 s8addq t1,a0,a5 d94: 00 90 d5 7e hw_stq/p t8,0(a5) d98: 00 40 ff 63 mb d9c: 02 00 e0 e5 beq fp,0xda8 da0: 56 ff df d3 bsr sp,0xafc da4: 01 00 e0 c3 br 0xdac da8: 5e ff df d3 bsr sp,0xb24 dac: 55 06 50 40 s8addq t1,a0,a5 db0: 13 04 b5 46 mov a5,a3 db4: 00 90 f5 6e hw_ldq/p t9,0(a5) db8: 18 08 f6 46 xor t9,t8,t10 dbc: 10 00 00 f7 bne t10,0xe00 dc0: 11 14 e1 47 mov 0x8,a1 dc4: 15 04 10 46 mov a0,a5 dc8: 16 04 ff 47 clr t8 dcc: a0 05 b3 42 cmpeq a5,a3,v0 dd0: 03 00 00 f4 bne v0,0xde0 dd4: 00 90 f5 6e hw_ldq/p t9,0(a5) dd8: 18 08 f6 46 xor t9,t8,t10 ddc: 08 00 00 f7 bne t10,0xe00 de0: 15 14 a1 42 addq a5,0x8,a5 de4: 31 35 20 42 subq a1,0x1,a1 de8: f8 ff 3f f6 bne a1,0xdcc dec: 23 37 60 48 sll t2,0x1,t2 df0: e6 ff 7f f4 bne t2,0xd8c df4: 02 34 40 40 addq t1,0x1,t1 df8: a3 13 41 40 cmpult t1,0x8,t2 dfc: da ff 7f f4 bne t2,0xd68 e00: 01 80 fc 6b ret zero,(at),0x1 e04: 65 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) e08: 04 34 e0 47 mov 0x1,t3 e0c: a0 09 a7 42 cmplt a5,t6,v0 e10: 04 00 00 e4 beq v0,0xe24 e14: 00 00 8a 44 and t3,s1,v0 e18: 07 00 00 f4 bne v0,0xe38 e1c: 24 37 80 48 sll t3,0x1,t3 e20: fc ff ff c3 br 0xe14 e24: 24 f7 85 48 sll t3,0x2f,t3 e28: 00 00 8a 44 and t3,s1,v0 e2c: 02 00 00 f4 bne v0,0xe38 e30: 84 36 80 48 srl t3,0x1,t3 e34: fc ff ff c3 br 0xe28 e38: 0b 04 64 45 or s2,t3,s2 e3c: 0a 01 44 45 andnot s1,t3,s1 e40: 02 00 40 f5 bne s1,0xe4c e44: fa 00 3f 23 lda t11,250 ; 0xfa e48: 54 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) e4c: 41 ff 7f d3 bsr t12,0xb54 e50: 6a ff ff c3 br 0xbfc ; DB - Initializing and testing the PCI bus, testing PCI bus data path e54: db 00 3f 23 lda t11,219 ; 0xdb e58: 50 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) e5c: 0f 00 ff 21 lda fp,15 e60: 0f 96 e0 49 zap fp,0x4,fp e64: 0a 00 1f 24 ldah v0,10 e68: 0f 04 0f 44 or v0,fp,fp e6c: 00 00 1f 22 lda a0,0 e70: b7 03 a0 d3 bsr gp,0x1d50 e74: 40 01 00 74 hw_mtpr v0,0x140 ; PALtemp0 e78: 86 80 df 22 lda t8,-32634 e7c: 83 04 d6 26 ldah t8,1155(t8) e80: 18 08 16 44 xor v0,t8,t10 e84: c9 03 c0 d3 bsr sp,0x1dac e88: 15 04 e1 47 mov t0,a5 e8c: 03 00 00 e7 beq t10,0xe9c e90: f8 00 3f 23 lda t11,248 ; 0xf8 e94: 40 01 f7 66 hw_mfpr t9,0x140 ; PALtemp0 e98: 40 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) e9c: 11 34 e0 47 mov 0x1,a1 ea0: 31 17 24 4a sll a1,0x20,a1 ea4: 60 00 1f 22 lda a0,96 ea8: 91 36 20 4a srl a1,0x1,a1 eac: 16 04 f1 47 mov a1,t8 eb0: b7 03 a0 d3 bsr gp,0x1d90 eb4: bd 03 c0 d3 bsr sp,0x1dac eb8: 15 04 e1 47 mov t0,a5 ebc: a4 03 a0 d3 bsr gp,0x1d50 ec0: 17 04 e0 47 mov v0,t9 ec4: 18 08 d7 46 xor t8,t9,t10 ec8: 02 00 00 e7 beq t10,0xed4 ecc: f8 00 3f 23 lda t11,248 ; 0xf8 ed0: 32 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) ed4: f4 ff 3f fe bgt a1,0xea8 ed8: d8 03 60 d3 bsr t12,0x1e3c ; Intel PCEB configuration on PCI bus edc: f5 03 60 d3 bsr t12,0x1eb4 ; System EISA I/O ports config ee0: 01 80 fa 6b ret ; CF - Loading flash ROM code ee4: cf 00 3f 23 lda t11,207 ; 0xcf ee8: 2c 02 a0 d3 bsr gp,0x179c ; diag_leds(t11) eec: 00 10 bf 21 lda s4,4096 ef0: 3f 00 3f 22 lda a1,63 ef4: 70 00 1f 22 lda a0,112 ef8: 9e 03 a0 d3 bsr gp,0x1d74 ; pci_io_write_byte(a0, a1) efc: 71 00 1f 22 lda a0,113 f00: 8c 03 a0 d3 bsr gp,0x1d34 ; v0 = pci_io_read_byte(a0) - Dallas RTC reg. 63 f04: a2 55 01 40 cmpeq v0,0xa,t1 ; is it 0xa? f08: 75 00 40 f4 bne t1,0x10e0 ; if yes, go to Floppy Boot f0c: 02 f0 00 44 and v0,0x7,t1 ; table index = (reg. 63) & 7 f10: 10 40 9f 20 lda t3,16400 f14: 40 40 84 24 ldah t3,16448(t3) f18: 24 17 84 48 sll t3,0x20,t3 f1c: 40 30 84 20 lda t3,12352(t3) f20: 40 40 84 24 ldah t3,16448(t3) ; 0x4040401040403040 - load address table f24: d0 00 82 48 extbl t3,t1,a0 ; a0 <- {4: 0x10, 1: 0x30, else 0x40}[(reg. 63) & 7] f28: 30 17 02 4a sll a0,0x10,a0 f2c: 0e 01 10 76 hw_mtpr a0,0x10e ; PAL_BASE - set at 1, 3, or 4 MB f30: 0f 0c 9f 20 lda t3,3087 f34: 0c 0c 84 24 ldah t3,3084(t3) f38: 24 17 84 48 sll t3,0x20,t3 f3c: 0c 0e 84 20 lda t3,3596(t3) f40: 0c 0c 84 24 ldah t3,3084(t3) ; 0x0c0c0c0f0c0c0e0c f44: c4 00 82 48 extbl t3,t1,t3 ; t3 <- {4: 0xf, 1: 0xe, else 0xc}[(reg. 63) & 7] f48: 24 17 81 48 sll t3,0x8,t3 f4c: 78 08 3f 22 lda a1,2168 f50: 31 97 23 4a sll a1,0x1c,a1 f54: 11 04 24 42 addq a1,t3,a1 ; a1 <- 87.8000.{0F00/0E00/0C00} resp. - flash ROM bank 3/2/0 f58: 05 04 ff 47 clr t4 f5c: 00 20 ae 22 lda a5,8192(s5) ; a5 <- 87.4000.2000 - CIA_DIAG f60: 01 00 df 22 lda t8,1 f64: dd 02 c0 d3 bsr sp,0x1adc ; stl_with_read_back(t8, a5) - enable write to flash f68: 15 04 31 46 mov a1,a5 f6c: 16 f4 ff 47 mov 0xff,t8 f70: da 02 c0 d3 bsr sp,0x1adc ; stl_with_read_back(t8, a5) - write ff to flash byte 0 f74: d9 02 c0 d3 bsr sp,0x1adc ; stl_with_read_back(t8, a5) f78: d8 02 c0 d3 bsr sp,0x1adc ; stl_with_read_back(t8, a5) f7c: 16 04 ff 47 clr t8 f80: d6 02 c0 d3 bsr sp,0x1adc ; stl_with_read_back(t8, a5) - write 00 to flash byte 0 f84: 00 20 ae 22 lda a5,8192(s5) f88: d4 02 c0 d3 bsr sp,0x1adc ; stl_with_read_back(t8, a5) - disable write to flash f8c: 08 00 5f 22 lda a2,8 f90: 29 00 60 d3 bsr t12,0x1038 f94: 55 00 df 22 lda t8,85 f98: aa ff d6 26 ldah t8,-86(t8) f9c: 36 f6 c1 4a zapnot t8,0xf,t8 ; t8 = 0xffaa0055 fa0: 18 08 f6 46 xor t9,t8,t10 fa4: 02 00 00 e7 beq t10,0xfb0 fa8: f1 00 3f 23 lda t11,241 ; 0xf1 - ROM data path read error fac: fb 01 a0 d3 bsr gp,0x179c ; diag_leds(t11) fb0: 00 1c ff 21 lda fp,7168 fb4: 43 06 af 40 s8addq t4,fp,t2 fb8: 40 00 5f 22 lda a2,64 fbc: 1e 00 60 d3 bsr t12,0x1038 fc0: 30 80 e3 7e hw_stl/p t9,48(t2) fc4: 2c 00 5f 22 lda a2,44 fc8: 1b 00 60 d3 bsr t12,0x1038 fcc: 37 36 e0 4a zapnot t9,0x1,t9 fd0: 34 80 e3 7e hw_stl/p t9,52(t2) fd4: 30 00 5f 22 lda a2,48 fd8: 17 00 60 d3 bsr t12,0x1038 ; t9 <- flash word at offset 48 fdc: 12 14 e8 42 addq t9,0x40,a2 ; length = t9 + 64 fe0: 15 00 60 d3 bsr t12,0x1038 ; load at a0, skip 64 bytes but include in checksum fe4: 23 37 a0 48 sll t4,0x1,t2 fe8: 05 34 a0 40 addq t4,0x1,t4 fec: a6 35 a0 40 cmpeq t4,0x1,t5 ff0: 0e 00 c0 e4 beq t5,0x102c ff4: 43 06 6f 40 s8addq t2,fp,t2 ff8: 16 04 00 44 mov v0,t8 ; t8 = calculated checksum ffc: ff ff bf 22 lda a5,-1 1000: 04 00 b5 26 ldah a5,4(a5) 1004: 35 97 a1 4a sll a5,0xc,a5 ; a5 = 0x3FFFF000 1008: 15 04 35 46 or a1,a5,a5 ; a5 <- last byte address in bank a1 100c: 00 80 f5 6e hw_ldl/p t9,0(a5) 1010: 37 36 e0 4a zapnot t9,0x1,t9 ; t9 <- last byte from ROM (checksum) 1014: 18 08 f6 46 xor t9,t8,t10 1018: 02 00 00 e7 beq t10,0x1024 101c: e0 00 3f 23 lda t11,224 ; 0xe0 - ROM checksum error 1020: de 01 a0 d3 bsr gp,0x179c ; diag_leds(t11) 1024: 48 90 c3 7e hw_stq/p t8,72(t2) ; store calculated checksum 1028: 40 90 e3 7e hw_stq/p t9,64(t2) ; store checksum from ROM 102c: 00 01 31 22 lda a1,256(a1) ; a1 <- next bank 1030: ca ff df e4 beq t5,0xf5c 1034: 01 80 fa 6b ret ; read_flash(a0, a1, a2) -> v0, t9 ; Inputs: a0 - destination memory address ; a1 - GRU flash rom bank address ; a2 - bytes to read (multiple of 4) ; Returns: v0 - checksum byte ; t9 - last word 1038: 15 04 31 46 mov a1,a5 103c: ff ff 1f 23 lda t10,-1 1040: 10 90 1f 7f hw_stq/p t10,16(zero) 1044: 00 04 ff 47 clr v0 1048: 40 00 7f 22 lda a3,64 ; don't write first 64 bytes to memory 104c: 33 95 60 42 subq a3,0x4,a3 1050: ff ff 1f 23 lda t10,-1 1054: 01 00 18 27 ldah t10,1(t10) 1058: 38 97 01 4b sll t10,0xc,t10 ; t10 = 0x0FFFF000 105c: 18 00 15 47 and t10,a5,t10 1060: 08 00 00 f7 bne t10,0x1084 1064: 10 90 1f 6f hw_ldq/p t10,16(zero) 1068: 18 34 00 43 addq t10,0x1,t10 106c: 01 90 00 47 and t10,0x4,t0 1070: 02 00 20 e4 beq t0,0x107c 1074: 00 01 31 22 lda a1,256(a1) ; a1 <- next bank 1078: 15 04 31 46 mov a1,a5 107c: 18 70 00 47 and t10,0x3,t10 1080: 10 90 1f 7f hw_stq/p t10,16(zero) 1084: 18 04 ff 47 clr t10 ; t0 = 0 - byte count in longword 1088: 17 04 ff 47 clr t9 ; t9 = 0 - longword accumulator 108c: 00 80 d5 6e hw_ldl/p t8,0(a5) ; t8 <- flash byte at a5 1090: 00 10 b5 22 lda a5,4096(a5) ; a5 <- next byte address 1094: 20 36 00 48 zapnot v0,0x1,v0 1098: 81 f6 00 48 srl v0,0x7,t0 109c: 20 37 00 48 sll v0,0x1,v0 10a0: 00 04 20 44 or t0,v0,v0 10a4: 00 04 16 40 addq v0,t8,v0 10a8: 20 36 00 48 zapnot v0,0x1,v0 ; update checksum in v0 with t8 10ac: 76 01 d8 4a insbl t8,t10,t8 10b0: 17 04 d7 46 or t8,t9,t9 ; insert byte into t9 10b4: 18 34 00 43 addq t10,0x1,t10 ; increment byte count 10b8: a1 93 00 43 cmpult t10,0x4,t0 ; byte count < 4? 10bc: f3 ff 3f f4 bne t0,0x108c ; if so, go back to get next byte 10c0: 02 00 60 fa bge a3,0x10cc 10c4: 00 80 f0 7e hw_stl/p t9,0(a0) ; store longword from flash at address a0 10c8: 10 94 00 42 addq a0,0x4,a0 ; a0 += 4 10cc: 32 95 40 42 subq a2,0x4,a2 ; decrease length to read by 4 10d0: de ff 5f fe bgt a2,0x104c ; if length > 0, go back to read next word 10d4: 01 80 fb 6b ret zero,(t12),0x1 10d8: c8 fe 5f d3 bsr ra,0xbfc 10dc: 93 fc 5f d3 bsr ra,0x32c 10e0: 4f fc 5f d3 bsr ra,0x220 10e4: 5b ff 5f d3 bsr ra,0xe54 ; DB - Init. and testing PCI bus and data path 10e8: 11 fc 5f d3 bsr ra,0x130 10ec: cd 00 3f 23 lda t11,205 ; 0xcd 10f0: aa 01 a0 d3 bsr gp,0x179c ; diag_leds(t11) 10f4: 0d 0a 7f 22 lda a3,2573 ; '\r\n' 10f8: ff 02 c0 d3 bsr sp,0x1cf8 ; sl_xmit_nc(a3) 10fc: 70 79 7f 22 lda a3,31088 1100: 20 00 73 26 ldah a3,32(a3) 1104: 33 17 64 4a sll a3,0x20,a3 1108: 46 6c 73 22 lda a3,27718(a3) 110c: 6f 70 73 26 ldah a3,28783(a3) ; 'Floppy ' 1110: f9 02 c0 d3 bsr sp,0x1cf8 ; sl_xmit_nc(a3) 1114: 0d 0a 7f 22 lda a3,2573 1118: 33 17 64 4a sll a3,0x20,a3 111c: 42 6f 73 22 lda a3,28482(a3) 1120: 6f 74 73 26 ldah a3,29807(a3) ; 'Boot\r\n' 1124: f4 02 c0 d3 bsr sp,0x1cf8 ; sl_xmit_nc(a3) 1128: 10 00 5f 26 ldah a2,16 112c: 41 64 7f 22 lda a3,25665 1130: 64 72 73 26 ldah a3,29284(a3) 1134: 33 17 64 4a sll a3,0x20,a3 1138: 4c 64 73 22 lda a3,25676(a3) ; 'LdAddr' (two NUL bytes between d and A) 113c: fa 02 c0 d3 bsr sp,0x1d28 ; print_name_and_longword_nc(a3, a2) 1140: 09 00 40 d3 bsr ra,0x1168 1144: 44 6f 7f 22 lda a3,28484 1148: 6e 65 73 26 ldah a3,25966(a3) 114c: 33 17 64 4a sll a3,0x20,a3 1150: 0d 0a 73 22 lda a3,2573(a3) ; '\r\nDone' (two NUL bytes after \n) 1154: e8 02 c0 d3 bsr sp,0x1cf8 ; sl_xmit_nc(a3) 1158: 0d 0a 7f 22 lda a3,2573 ; '\r\n' 115c: e6 02 c0 d3 bsr sp,0x1cf8 ; sl_xmit_nc(a3) 1160: 4c fc 5f d3 bsr ra,0x294 1164: 00 80 ff 7b hw_rei 1168: 76 08 5f 20 lda t1,2166 116c: 22 97 43 48 sll t1,0x1c,t1 1170: f0 3f 1f 24 ldah v0,16368 1174: 40 04 22 20 lda t0,1088(t1) 1178: 00 80 01 7c hw_stl/p v0,0(t0) 117c: 00 40 ff 63 mb 1180: 80 04 22 20 lda t0,1152(t1) 1184: 00 80 e1 7f hw_stl/p zero,0(t0) 1188: 00 40 ff 63 mb 118c: 00 40 1f 24 ldah v0,16384 1190: 00 34 00 44 or v0,0x1,v0 1194: 00 04 22 20 lda t0,1024(t1) 1198: 00 80 01 7c hw_stl/p v0,0(t0) 119c: 00 40 ff 63 mb 11a0: 00 20 5f 20 lda t1,8192 11a4: 24 80 e2 7f hw_stl/p zero,36(t1) 11a8: 02 00 1f 20 lda v0,2 11ac: 0c 80 02 7c hw_stl/p v0,12(t1) 11b0: 12 00 1f 20 lda v0,18 11b4: 08 80 02 7c hw_stl/p v0,8(t1) 11b8: c0 00 1f 20 lda v0,192 11bc: 18 80 02 7c hw_stl/p v0,24(t1) 11c0: 0f 00 1f 20 lda v0,15 11c4: 1c 80 02 7c hw_stl/p v0,28(t1) 11c8: ff ff 1f 20 lda v0,-1 11cc: 20 80 02 7c hw_stl/p v0,32(t1) 11d0: 08 00 ff 21 lda fp,8 11d4: 41 01 00 d3 bsr t10,0x16dc 11d8: f2 03 1f 22 lda a0,1010 11dc: 08 00 3f 22 lda a1,8 11e0: eb 02 a0 d3 bsr gp,0x1d90 11e4: 0a 00 1f 22 lda a0,10 11e8: 30 01 00 d3 bsr t10,0x16ac 11ec: f2 03 1f 22 lda a0,1010 11f0: 0c 00 3f 22 lda a1,12 11f4: e6 02 a0 d3 bsr gp,0x1d90 11f8: f4 03 1f 22 lda a0,1012 11fc: d4 02 a0 d3 bsr gp,0x1d50 1200: 01 10 10 44 and v0,0x80,t0 1204: 0b 00 20 f4 bne t0,0x1234 1208: f4 03 1f 22 lda a0,1012 120c: 80 00 3f 22 lda a1,128 1210: df 02 a0 d3 bsr gp,0x1d90 1214: 01 00 1f 22 lda a0,1 1218: 24 01 00 d3 bsr t10,0x16ac 121c: f2 03 1f 22 lda a0,1010 1220: 0c 00 3f 22 lda a1,12 1224: da 02 a0 d3 bsr gp,0x1d90 1228: f4 03 1f 22 lda a0,1012 122c: c8 02 a0 d3 bsr gp,0x1d50 1230: f3 ff ff c3 br 0x1200 1234: f7 03 1f 22 lda a0,1015 1238: 00 00 3f 22 lda a1,0 123c: d4 02 a0 d3 bsr gp,0x1d90 1240: 08 00 1f 22 lda a0,8 1244: 01 00 5f 22 lda a2,1 1248: d3 00 80 d3 bsr at,0x1598 124c: e7 00 80 d3 bsr at,0x15ec 1250: 03 00 1f 22 lda a0,3 1254: 18 80 02 6c hw_ldl/p v0,24(t1) 1258: 1c 80 22 6c hw_ldl/p t0,28(t1) 125c: 00 04 01 44 or v0,t0,v0 1260: 60 31 00 48 insbl v0,0x1,v0 1264: 10 04 10 44 or v0,a0,a0 1268: 02 00 1f 20 lda v0,2 126c: 60 51 00 48 insbl v0,0x2,v0 1270: 10 04 10 44 or v0,a0,a0 1274: 03 00 5f 22 lda a2,3 1278: c7 00 80 d3 bsr at,0x1598 127c: f2 03 1f 22 lda a0,1010 1280: 1c 00 3f 22 lda a1,28 1284: c2 02 a0 d3 bsr gp,0x1d90 1288: d0 07 1f 22 lda a0,2000 128c: 07 01 00 d3 bsr t10,0x16ac 1290: 00 00 1f 22 lda a0,0 1294: 00 fe 9f 20 lda t3,-512 1298: 10 00 84 24 ldah t3,16(t3) 129c: 11 04 9f 44 or t3,zero,a1 12a0: 2e 00 60 d3 bsr t12,0x135c 12a4: f8 91 c4 6c hw_ldq/p t5,504(t3) 12a8: 3f 00 1f 20 lda v0,63 12ac: 11 04 ff 47 clr a1 12b0: 12 04 9f 44 or t3,zero,a2 12b4: 00 90 32 6c hw_ldq/p t0,0(a2) 12b8: 11 04 31 40 addq t0,a1,a1 12bc: 12 14 41 42 addq a2,0x8,a2 12c0: 20 35 00 40 subq v0,0x1,v0 12c4: fb ff 1f f4 bne v0,0x12b4 12c8: 21 05 26 42 subq a1,t5,t0 12cc: 05 00 20 e4 beq t0,0x12e4 12d0: f2 03 1f 22 lda a0,1010 12d4: 0c 00 3f 22 lda a1,12 12d8: ad 02 a0 d3 bsr gp,0x1d90 12dc: fd 00 3f 23 lda t11,253 ; 0xfd 12e0: 2e 01 a0 d3 bsr gp,0x179c ; diag_leds(t11) 12e4: 00 fe 1f 22 lda a0,-512 12e8: 10 00 10 26 ldah a0,16(a0) 12ec: e8 91 70 6c hw_ldq/p t2,488(a0) 12f0: e0 91 b0 6c hw_ldq/p t4,480(a0) 12f4: 12 04 63 44 mov t2,a2 12f8: 4c 42 7f 22 lda a3,16972 12fc: 4e 3a 73 26 ldah a3,14926(a3) ; 'LBN:' 1300: 89 02 c0 d3 bsr sp,0x1d28 ; print_name_and_longword_nc(a3, a2) 1304: 12 04 a5 44 mov t4,a2 1308: 43 6e 7f 22 lda a3,28227 130c: 74 3a 73 26 ldah a3,14964(a3) ; 'Cnt:' 1310: 85 02 c0 d3 bsr sp,0x1d28 ; print_name_and_longword_nc(a3, a2) 1314: 10 00 9f 24 ldah t3,16 1318: 0e 01 84 74 hw_mtpr t3,0x10e ; PAL_BASE 131c: ff 3f 1f 20 lda v0,16383 1320: 00 00 04 44 and v0,t3,v0 1324: 02 00 00 f4 bne v0,0x1330 1328: 2e 00 1f 22 lda a0,46 132c: 6f 02 c0 d3 bsr sp,0x1cec ; sl_xmit_byte_nc(a0) 1330: 10 04 7f 44 or t2,zero,a0 1334: 11 04 9f 44 or t3,zero,a1 1338: 08 00 60 d3 bsr t12,0x135c 133c: 03 34 60 40 addq t2,0x1,t2 1340: 00 02 84 20 lda t3,512(t3) 1344: 25 35 a0 40 subq t4,0x1,t4 1348: f4 ff bf f4 bne t4,0x131c 134c: f2 03 1f 22 lda a0,1010 1350: 0c 00 3f 22 lda a1,12 1354: 8e 02 a0 d3 bsr gp,0x1d90 1358: 01 80 fa 6b ret 135c: 34 80 02 7e hw_stl/p a0,52(t1) 1360: 38 80 22 7e hw_stl/p a1,56(t1) 1364: 01 00 bf 21 lda s4,1 1368: 09 04 ff 47 clr s0 136c: 24 80 02 6c hw_ldl/p v0,36(t1) 1370: 88 00 00 e8 blt v0,0x1594 1374: 87 00 a0 e5 beq s4,0x1594 1378: a0 59 20 41 cmplt s0,0x2,v0 137c: 85 00 00 e4 beq v0,0x1594 1380: 20 80 02 6c hw_ldl/p v0,32(t1) 1384: 13 00 00 f8 bge v0,0x13d4 1388: 07 00 1f 20 lda v0,7 138c: 70 11 00 48 insbl v0,0,a0 1390: 02 00 5f 22 lda a2,2 1394: 80 00 80 d3 bsr at,0x1598 1398: 10 04 ff 47 clr a0 139c: af 00 00 d3 bsr t10,0x165c 13a0: 08 00 1f 22 lda a0,8 13a4: 01 00 3f 22 lda a1,1 13a8: 7b 00 80 d3 bsr at,0x1598 13ac: 8f 00 80 d3 bsr at,0x15ec 13b0: 05 00 00 e4 beq v0,0x13c8 13b4: 0e 34 c0 41 addq s5,0x1,s5 13b8: a0 59 c0 41 cmplt s5,0x2,v0 13bc: f2 ff 1f f4 bne v0,0x1388 13c0: 01 00 1f 20 lda v0,1 13c4: 01 80 fb 6b ret zero,(t12),0x1 13c8: 20 80 e2 7f hw_stl/p zero,32(t1) 13cc: 0f 00 1f 22 lda a0,15 13d0: b6 00 00 d3 bsr t10,0x16ac 13d4: 0a 04 ff 47 clr s1 13d8: 08 80 02 6c hw_ldl/p v0,8(t1) 13dc: 0c 80 22 6c hw_ldl/p t0,12(t1) 13e0: 11 00 20 4c mull t0,v0,a1 13e4: 34 80 02 6e hw_ldl/p a0,52(t1) 13e8: 73 01 c0 d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 13ec: 0b 04 1f 44 or v0,zero,s2 13f0: 0c 04 3f 44 or t0,zero,s3 13f4: 08 80 02 6c hw_ldl/p v0,8(t1) 13f8: a1 09 80 41 cmplt s3,v0,t0 13fc: 02 00 20 f4 bne t0,0x1408 1400: 0a 34 40 41 addq s1,0x1,s1 1404: 2c 05 80 41 subq s3,v0,s3 1408: 20 80 02 6c hw_ldl/p v0,32(t1) 140c: a0 05 60 41 cmpeq s2,v0,v0 1410: 13 00 00 f4 bne v0,0x1460 1414: 0f 00 1f 22 lda a0,15 1418: 20 57 40 49 sll s1,0x2,v0 141c: 60 31 00 48 insbl v0,0x1,v0 1420: 10 04 10 44 or v0,a0,a0 1424: 60 51 60 49 insbl s2,0x2,v0 1428: 10 04 10 44 or v0,a0,a0 142c: 03 00 5f 22 lda a2,3 1430: 59 00 80 d3 bsr at,0x1598 1434: 10 00 1f 26 ldah a0,16 1438: 88 00 00 d3 bsr t10,0x165c 143c: 08 00 1f 22 lda a0,8 1440: 01 00 5f 22 lda a2,1 1444: 54 00 80 d3 bsr at,0x1598 1448: 68 00 80 d3 bsr at,0x15ec 144c: 01 00 00 e4 beq v0,0x1454 1450: 01 80 fb 6b ret zero,(t12),0x1 1454: 20 80 62 7d hw_stl/p s2,32(t1) 1458: 0f 00 1f 22 lda a0,15 145c: 93 00 00 d3 bsr t10,0x16ac 1460: d0 00 1f 22 lda a0,208 1464: 00 00 3f 22 lda a1,0 1468: 49 02 a0 d3 bsr gp,0x1d90 146c: 08 00 1f 22 lda a0,8 1470: 00 00 3f 22 lda a1,0 1474: 46 02 a0 d3 bsr gp,0x1d90 1478: d6 00 1f 22 lda a0,214 147c: c0 00 3f 22 lda a1,192 1480: 43 02 a0 d3 bsr gp,0x1d90 1484: 0b 00 1f 22 lda a0,11 1488: 46 00 3f 22 lda a1,70 148c: 40 02 a0 d3 bsr gp,0x1d90 1490: 0b 04 1f 22 lda a0,1035 1494: 02 00 3f 22 lda a1,2 1498: 3d 02 a0 d3 bsr gp,0x1d90 149c: 0c 00 1f 22 lda a0,12 14a0: 00 00 3f 22 lda a1,0 14a4: 3a 02 a0 d3 bsr gp,0x1d90 14a8: 38 80 c2 6e hw_ldl/p t8,56(t1) 14ac: d1 10 c0 4a extbl t8,0,a1 14b0: 04 00 1f 22 lda a0,4 14b4: 36 02 a0 d3 bsr gp,0x1d90 14b8: d1 30 c0 4a extbl t8,0x1,a1 14bc: 34 02 a0 d3 bsr gp,0x1d90 14c0: d1 50 c0 4a extbl t8,0x2,a1 14c4: 81 00 1f 22 lda a0,129 14c8: 31 02 a0 d3 bsr gp,0x1d90 14cc: 11 14 e8 47 mov 0x40,a1 14d0: 81 04 1f 22 lda a0,1153 14d4: 2e 02 a0 d3 bsr gp,0x1d90 14d8: 0c 00 1f 22 lda a0,12 14dc: 00 00 3f 22 lda a1,0 14e0: 2b 02 a0 d3 bsr gp,0x1d90 14e4: ff 00 3f 22 lda a1,255 14e8: 05 00 1f 22 lda a0,5 14ec: 28 02 a0 d3 bsr gp,0x1d90 14f0: 01 00 3f 22 lda a1,1 14f4: 26 02 a0 d3 bsr gp,0x1d90 14f8: 00 00 3f 22 lda a1,0 14fc: 05 04 1f 22 lda a0,1029 1500: 23 02 a0 d3 bsr gp,0x1d90 1504: d4 00 1f 22 lda a0,212 1508: 00 00 3f 22 lda a1,0 150c: 20 02 a0 d3 bsr gp,0x1d90 1510: 0a 00 1f 22 lda a0,10 1514: 02 00 3f 22 lda a1,2 1518: 1d 02 a0 d3 bsr gp,0x1d90 151c: 66 00 1f 22 lda a0,102 1520: 20 57 40 49 sll s1,0x2,v0 1524: 60 31 00 48 insbl v0,0x1,v0 1528: 10 04 10 44 or v0,a0,a0 152c: 60 51 60 49 insbl s2,0x2,v0 1530: 10 04 10 44 or v0,a0,a0 1534: 60 71 40 49 insbl s1,0x3,v0 1538: 10 04 10 44 or v0,a0,a0 153c: 00 34 80 41 addq s3,0x1,v0 1540: 60 91 00 48 insbl v0,0x4,v0 1544: 10 04 10 44 or v0,a0,a0 1548: 02 00 1f 20 lda v0,2 154c: 60 b1 00 48 insbl v0,0x5,v0 1550: 10 04 10 44 or v0,a0,a0 1554: 08 80 02 6c hw_ldl/p v0,8(t1) 1558: 60 d1 00 48 insbl v0,0x6,v0 155c: 10 04 10 44 or v0,a0,a0 1560: 1b 00 1f 20 lda v0,27 1564: 60 f1 00 48 insbl v0,0x7,v0 1568: 10 04 10 44 or v0,a0,a0 156c: ff 00 3f 22 lda a1,255 1570: 09 00 5f 22 lda a2,9 1574: 08 00 80 d3 bsr at,0x1598 1578: 10 00 1f 26 ldah a0,16 157c: 37 00 00 d3 bsr t10,0x165c 1580: 04 00 00 f4 bne v0,0x1594 1584: 19 00 80 d3 bsr at,0x15ec 1588: 02 00 00 e4 beq v0,0x1594 158c: 09 34 20 41 addq s0,0x1,s0 1590: 76 ff ff c3 br 0x136c 1594: 01 80 fb 6b ret zero,(t12),0x1 1598: 14 04 1f 46 or a0,zero,a4 159c: 15 04 3f 46 or a1,zero,a5 15a0: 13 04 ff 47 clr a3 15a4: a0 09 72 42 cmplt a3,a2,v0 15a8: 0f 00 00 e4 beq v0,0x15e8 15ac: f4 03 1f 22 lda a0,1012 15b0: e7 01 a0 d3 bsr gp,0x1d50 15b4: 01 10 18 44 and v0,0xc0,t0 15b8: a0 15 30 40 cmpeq t0,0x80,v0 15bc: fb ff 1f e4 beq v0,0x15ac 15c0: a0 19 61 42 cmplt a3,0x8,v0 15c4: 02 00 00 e4 beq v0,0x15d0 15c8: d1 00 93 4a extbl a4,a3,a1 15cc: 02 00 e0 c3 br 0x15d8 15d0: 21 15 61 42 subq a3,0x8,t0 15d4: d1 00 a1 4a extbl a5,t0,a1 15d8: f5 03 1f 22 lda a0,1013 15dc: ec 01 a0 d3 bsr gp,0x1d90 15e0: 13 34 60 42 addq a3,0x1,a3 15e4: ef ff ff c3 br 0x15a4 15e8: 01 80 fc 6b ret zero,(at),0x1 15ec: 13 04 ff 47 clr a3 15f0: 12 04 ff 47 clr a2 15f4: f4 03 1f 22 lda a0,1012 15f8: d5 01 a0 d3 bsr gp,0x1d50 15fc: 01 10 10 44 and v0,0x80,t0 1600: fc ff 3f e4 beq t0,0x15f4 1604: 01 10 08 44 and v0,0x40,t0 1608: 08 00 20 e4 beq t0,0x162c 160c: f5 03 1f 22 lda a0,1013 1610: cf 01 a0 d3 bsr gp,0x1d50 1614: a1 f9 40 42 cmplt a2,0x7,t0 1618: 02 00 20 e4 beq t0,0x1624 161c: 60 01 12 48 insbl v0,a2,v0 1620: 13 04 13 44 or v0,a3,a3 1624: 12 34 40 42 addq a2,0x1,a2 1628: f2 ff ff c3 br 0x15f4 162c: c1 10 60 4a extbl a3,0,t0 1630: 01 10 38 44 and t0,0xc0,t0 1634: a1 15 20 40 cmpeq t0,0,t0 1638: 04 00 20 f4 bne t0,0x164c 163c: ff ff 1f 20 lda v0,-1 1640: 20 80 02 7c hw_stl/p v0,32(t1) 1644: 01 00 1f 20 lda v0,1 1648: 01 80 fc 6b ret zero,(at),0x1 164c: 24 80 02 6c hw_ldl/p v0,36(t1) 1650: fa ff 1f e8 blt v0,0x163c 1654: 00 04 ff 47 clr v0 1658: 01 80 fc 6b ret zero,(at),0x1 165c: 12 04 1f 46 or a0,zero,a2 1660: 13 04 ff 47 clr a3 1664: 24 80 e2 7f hw_stl/p zero,36(t1) 1668: 20 00 1f 22 lda a0,32 166c: 0a 00 3f 22 lda a1,10 1670: c7 01 a0 d3 bsr gp,0x1d90 1674: 20 00 1f 22 lda a0,32 1678: b5 01 a0 d3 bsr gp,0x1d50 167c: 07 00 40 e6 beq a2,0x169c 1680: 13 34 60 42 addq a3,0x1,a3 1684: a1 05 72 42 cmpeq a3,a2,t0 1688: 04 00 20 e4 beq t0,0x169c 168c: ff ff 3f 20 lda t0,-1 1690: 24 80 22 7c hw_stl/p t0,36(t1) 1694: 01 00 3f 20 lda t0,1 1698: 01 80 f8 6b ret zero,(t10),0x1 169c: 01 10 08 44 and v0,0x40,t0 16a0: f1 ff 3f e4 beq t0,0x1668 16a4: 00 04 ff 47 clr v0 16a8: 01 80 f8 6b ret zero,(t10),0x1 16ac: 56 01 00 64 hw_mfpr v0,0x156 ; PALtemp22 16b0: c0 94 00 48 extll v0,0x4,v0 16b4: 20 57 01 48 sll v0,0xa,v0 16b8: 00 04 10 4c mulq v0,a0,v0 16bc: 01 00 3f 20 lda t0,1 16c0: 21 17 24 48 sll t0,0x20,t0 16c4: 0e 02 21 74 hw_mtpr t0,0x20e ; CC_CTL 16c8: 21 f6 21 48 zapnot t0,0xf,t0 16cc: b0 09 01 40 cmplt v0,t0,a0 16d0: 00 c0 3f 60 rpcc t0 16d4: fc ff 1f e6 beq a0,0x16c8 16d8: 01 80 f8 6b ret zero,(t10),0x1 16dc: a0 00 1f 22 lda a0,160 16e0: 11 00 3f 22 lda a1,17 16e4: aa 01 a0 d3 bsr gp,0x1d90 16e8: a1 00 1f 22 lda a0,161 16ec: 08 00 3f 22 lda a1,8 16f0: a7 01 a0 d3 bsr gp,0x1d90 16f4: a1 00 1f 22 lda a0,161 16f8: 02 00 3f 22 lda a1,2 16fc: a4 01 a0 d3 bsr gp,0x1d90 1700: a1 00 1f 22 lda a0,161 1704: 01 00 3f 22 lda a1,1 1708: a1 01 a0 d3 bsr gp,0x1d90 170c: a1 00 1f 22 lda a0,161 1710: 00 00 3f 22 lda a1,0 1714: 9e 01 a0 d3 bsr gp,0x1d90 1718: d1 04 1f 22 lda a0,1233 171c: 00 00 3f 22 lda a1,0 1720: 9b 01 a0 d3 bsr gp,0x1d90 1724: 20 00 1f 22 lda a0,32 1728: 11 00 3f 22 lda a1,17 172c: 98 01 a0 d3 bsr gp,0x1d90 1730: 21 00 1f 22 lda a0,33 1734: 00 00 3f 22 lda a1,0 1738: 95 01 a0 d3 bsr gp,0x1d90 173c: 21 00 1f 22 lda a0,33 1740: 04 00 3f 22 lda a1,4 1744: 92 01 a0 d3 bsr gp,0x1d90 1748: 21 00 1f 22 lda a0,33 174c: 01 00 3f 22 lda a1,1 1750: 8f 01 a0 d3 bsr gp,0x1d90 1754: 21 00 1f 22 lda a0,33 1758: fb 00 3f 22 lda a1,251 175c: 8c 01 a0 d3 bsr gp,0x1d90 1760: d1 04 1f 22 lda a0,1233 1764: 04 00 3f 22 lda a1,4 1768: 89 01 a0 d3 bsr gp,0x1d90 176c: 12 04 ff 47 clr a2 1770: 20 00 7f 22 lda a3,32 1774: 11 04 53 46 or a2,a3,a1 1778: a0 00 1f 22 lda a0,160 177c: 84 01 a0 d3 bsr gp,0x1d90 1780: 11 04 53 46 or a2,a3,a1 1784: 20 00 1f 22 lda a0,32 1788: 81 01 a0 d3 bsr gp,0x1d90 178c: 12 34 40 42 addq a2,0x1,a2 1790: a0 19 41 42 cmplt a2,0x8,v0 1794: f7 ff 1f f4 bne v0,0x1774 1798: 01 80 f8 6b ret zero,(t10),0x1 ; diag_leds(t11) ; Display a code on the diagnostic LEDs (or Flamingo LSM). ; Output something to the SROM diag port, if enabled. ; Input: t11 - code to display. 179c: 01 00 20 f7 bne t11,0x17a4 17a0: 01 80 fd 6b ret zero,(gp),0x1 17a4: 52 01 52 76 hw_mtpr a2,0x152 ; PALtemp18 17a8: 53 01 73 76 hw_mtpr a3,0x153 ; PALtemp19 17ac: 54 01 10 76 hw_mtpr a0,0x154 ; PALtemp20 17b0: 55 01 31 76 hw_mtpr a1,0x155 ; PALtemp21 17b4: 56 01 52 66 hw_mfpr a2,0x156 ; PALtemp22 17b8: d2 30 40 4a extbl a2,0x1,a2 17bc: 06 00 40 f2 blbs a2,0x17d8 17c0: 08 00 7f 22 lda a3,8 17c4: 80 87 73 26 ldah a3,-30848(a3) 17c8: 33 f6 61 4a zapnot a3,0xf,a3 17cc: 33 17 61 4a sll a3,0x8,a3 17d0: 00 80 33 7f hw_stl/p t11,0(a3) 17d4: 00 40 ff 63 mb 17d8: b3 13 3c 43 cmpult t11,0xe0,a3 17dc: 07 00 60 e6 beq a3,0x17fc 17e0: 11 04 39 47 mov t11,a1 17e4: 47 01 c0 d3 bsr sp,0x1d04 ; print_hex_byte_nc(a1) 17e8: 2e 00 1f 22 lda a0,46 17ec: 3f 01 c0 d3 bsr sp,0x1cec ; sl_xmit_byte_nc(a0) 17f0: b3 b5 39 43 cmpeq t11,0xcd,a3 17f4: 2c 00 60 f6 bne a3,0x18a8 17f8: 5a 00 e0 c3 br 0x1964 17fc: 18 01 52 66 hw_mfpr a2,0x118 ; ICSR 1800: 10 34 00 46 or a0,0x1,a0 1804: 30 f7 04 4a sll a0,0x27,a0 1808: 12 04 50 46 or a2,a0,a2 180c: 18 01 52 76 hw_mtpr a2,0x118 ; ICSR 1810: 01 00 5f 22 lda a2,1 1814: 56 01 10 66 hw_mfpr a0,0x156 ; PALtemp22 1818: 10 04 50 46 or a2,a0,a0 181c: 56 01 10 76 hw_mtpr a0,0x156 ; PALtemp22 1820: 32 17 27 4b sll t11,0x38,a2 1824: 12 04 b2 47 or gp,a2,a2 1828: 71 2f 7f 22 lda a3,12145 182c: 50 43 73 26 ldah a3,17232(a3) 1830: 33 17 64 4a sll a3,0x20,a3 1834: 0d 0a 73 22 lda a3,2573(a3) 1838: 53 65 73 26 ldah a3,25939(a3) ; '\r\nSeq/PC' 183c: 37 01 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 1840: 12 f0 21 47 and t11,0xf,a2 1844: b2 53 41 42 cmpult a2,0xa,a2 1848: 46 00 40 e6 beq a2,0x1964 184c: 45 00 00 e7 beq t10,0x1964 1850: 12 04 b5 46 mov a5,a2 1854: 41 64 7f 22 lda a3,25665 1858: 64 72 73 26 ldah a3,29284(a3) ; 'Addr' 185c: 2f 01 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 1860: 12 04 f7 46 mov t9,a2 1864: 52 65 7f 22 lda a3,25938 1868: 63 00 73 26 ldah a3,99(a3) 186c: 33 17 64 4a sll a3,0x20,a3 1870: 44 61 73 22 lda a3,24900(a3) 1874: 74 61 73 26 ldah a3,24948(a3) ; 'DataRec' 1878: 28 01 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 187c: 12 04 d6 46 mov t8,a2 1880: 45 78 7f 22 lda a3,30789 1884: 70 00 73 26 ldah a3,112(a3) 1888: 33 17 64 4a sll a3,0x20,a3 188c: 44 61 73 22 lda a3,24900(a3) 1890: 74 61 73 26 ldah a3,24948(a3) ; 'DataExp' 1894: 21 01 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 1898: 12 04 18 47 mov t10,a2 189c: 58 4f 7f 22 lda a3,20312 18a0: 52 00 73 26 ldah a3,82(a3) ; 'XOR' 18a4: 1d 01 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 18a8: 0d 0a 7f 22 lda a3,2573 ; '\r\n' 18ac: 12 01 c0 d3 bsr sp,0x1cf8 ; sl_xmit_nc(a3) 18b0: 30 90 ef 6c hw_ldq/p t6,48(fp) 18b4: 12 04 e7 44 mov t6,a2 18b8: 52 4f 7f 22 lda a3,20306 18bc: 4d 00 73 26 ldah a3,77(a3) 18c0: 33 17 64 4a sll a3,0x20,a3 18c4: 73 79 73 22 lda a3,31091(a3) 18c8: 73 00 73 26 ldah a3,115(a3) ; 'sysROM' (NUL byte after sys) 18cc: 13 01 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 18d0: 12 04 4a 45 mov s1,a2 18d4: 4d 65 7f 22 lda a3,25933 18d8: 6d 00 73 26 ldah a3,109(a3) 18dc: 33 17 64 4a sll a3,0x20,a3 18e0: 63 66 73 22 lda a3,26211(a3) 18e4: 67 64 73 26 ldah a3,25703(a3) ; 'cfgdMem' 18e8: 0c 01 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 18ec: 07 00 60 e5 beq s2,0x190c 18f0: 12 04 6b 45 mov s2,a2 18f4: 4d 65 7f 22 lda a3,25933 18f8: 6d 00 73 26 ldah a3,109(a3) 18fc: 33 17 64 4a sll a3,0x20,a3 1900: 62 61 73 22 lda a3,24930(a3) 1904: 64 00 73 26 ldah a3,100(a3) ; 'badMem' (NUL byte after bad) 1908: 04 01 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 190c: 12 04 8c 45 mov s3,a2 1910: 4d 42 7f 22 lda a3,16973 1914: 33 17 64 4a sll a3,0x20,a3 1918: 63 66 73 22 lda a3,26211(a3) 191c: 67 64 73 26 ldah a3,25703(a3) ; 'cfgdMB' 1920: fe 00 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 1924: 12 04 08 45 mov t7,a2 1928: 63 6e 7f 22 lda a3,28259 192c: 66 67 73 26 ldah a3,26470(a3) 1930: 33 17 64 4a sll a3,0x20,a3 1934: 62 63 73 22 lda a3,25442(a3) 1938: 5f 00 73 26 ldah a3,95(a3) ; 'bc_cnfg' (NUL byte after _) 193c: f7 00 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 1940: 12 04 29 45 mov s0,a2 1944: 63 6e 7f 22 lda a3,28259 1948: 74 6c 73 26 ldah a3,27764(a3) 194c: 33 17 64 4a sll a3,0x20,a3 1950: 62 63 73 22 lda a3,25442(a3) 1954: 5f 00 73 26 ldah a3,95(a3) ; 'bc_cntl' (NUL byte after _) 1958: f0 00 c0 d3 bsr sp,0x1d1c ; print_name_and_quadword_nc(a3, a2) 195c: 0d 0a 7f 22 lda a3,2573 ; '\r\n' 1960: e5 00 c0 d3 bsr sp,0x1cf8 ; sl_xmit_nc(a3) 1964: 18 01 52 66 hw_mfpr a2,0x118 ; ICSR 1968: 10 34 00 46 or a0,0x1,a0 196c: 30 f7 04 4a sll a0,0x27,a0 1970: 12 01 50 46 andnot a2,a0,a2 1974: 18 01 52 76 hw_mtpr a2,0x118 ; ICSR 1978: b3 35 3e 43 cmpeq t11,0xf1,a3 197c: d8 fd 7f f6 bne a3,0x10e0 1980: b3 13 3e 43 cmpult t11,0xf0,a3 1984: 06 00 60 f6 bne a3,0x19a0 1988: 0d 0a 7f 22 lda a3,2573 ; CR LF 198c: 33 17 64 4a sll a3,0x20,a3 1990: 48 41 73 22 lda a3,16712(a3) ; 'HA' 1994: 4c 54 73 26 ldah a3,21580(a3) ; 'LT' 1998: ad 00 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) - 'HALT\r\n' 199c: ff ff ff c3 br 0x199c ; stop here 19a0: 54 01 10 66 hw_mfpr a0,0x154 ; PALtemp20 19a4: 55 01 31 66 hw_mfpr a1,0x155 ; PALtemp21 19a8: 52 01 52 66 hw_mfpr a2,0x152 ; PALtemp18 19ac: 53 01 73 66 hw_mfpr a3,0x153 ; PALtemp19 19b0: 1f 04 ff 47 nop 19b4: 01 80 fd 6b ret zero,(gp),0x1 ; Division. ; v0, t0 = a0 / a1 19b8: 14 00 20 e6 beq a1,0x1a0c 19bc: 00 04 ff 47 clr v0 19c0: b5 03 11 42 cmpult a0,a1,a5 19c4: 13 00 a0 f6 bne a5,0x1a14 19c8: 17 04 10 46 mov a0,t9 19cc: 18 04 31 46 mov a1,t10 19d0: 16 04 ff 47 clr t8 19d4: 15 34 e0 47 mov 0x1,a5 19d8: 21 05 f8 42 subq t9,t10,t0 19dc: 16 34 c0 42 addq t8,0x1,t8 19e0: 38 37 00 4b sll t10,0x1,t10 19e4: fc ff 3f f8 bge t0,0x19d8 19e8: 36 55 c0 42 subq t8,0x2,t8 19ec: 98 56 00 4b srl t10,0x2,t10 19f0: 35 07 b6 4a sll a5,t8,a5 19f4: 00 04 a0 46 or a5,v0,v0 19f8: 37 05 f8 42 subq t9,t10,t9 19fc: a1 07 37 42 cmpule a1,t9,t0 1a00: f2 ff 3f f4 bne t0,0x19cc 1a04: 01 04 f7 46 mov t9,t0 1a08: 01 80 fe 6b ret zero,(sp),0x1 1a0c: ff ff 1f 20 lda v0,-1 1a10: 01 80 fe 6b ret zero,(sp),0x1 1a14: 01 04 10 46 mov a0,t0 1a18: 01 80 fe 6b ret zero,(sp),0x1 1a1c: e6 ff df d3 bsr sp,0x19b8 ; v0, t0 = a0 / a1 1a20: 01 00 20 e4 beq t0,0x1a28 1a24: 00 34 00 40 addq v0,0x1,v0 1a28: 01 80 fd 6b ret zero,(gp),0x1 1a2c: 15 04 10 46 mov a0,a5 1a30: 00 90 b5 7e hw_stq/p a5,0(a5) 1a34: 00 40 ff 63 mb 1a38: 95 34 a0 46 cmoveq a5,0x1,a5 1a3c: 35 37 a0 4a sll a5,0x1,a5 1a40: a0 03 b1 42 cmpult a5,a1,v0 1a44: fa ff 1f f4 bne v0,0x1a30 1a48: 15 04 10 46 mov a0,a5 1a4c: 16 04 b5 46 mov a5,t8 1a50: 00 90 f5 6e hw_ldq/p t9,0(a5) 1a54: 18 08 f6 46 xor t9,t8,t10 1a58: 04 00 00 f7 bne t10,0x1a6c 1a5c: 95 34 a0 46 cmoveq a5,0x1,a5 1a60: 35 37 a0 4a sll a5,0x1,a5 1a64: a0 03 b1 42 cmpult a5,a1,v0 1a68: f8 ff 1f f4 bne v0,0x1a4c 1a6c: 01 80 fe 6b ret zero,(sp),0x1 1a70: 15 04 10 46 mov a0,a5 1a74: 14 04 31 46 mov a1,a4 1a78: d6 04 55 46 cmovne a2,a5,t8 1a7c: 00 90 d5 7e hw_stq/p t8,0(a5) 1a80: 00 40 ff 63 mb 1a84: 15 14 a1 42 addq a5,0x8,a5 1a88: 34 35 80 42 subq a4,0x1,a4 1a8c: fa ff 9f fe bgt a4,0x1a78 1a90: 01 80 fe 6b ret zero,(sp),0x1 1a94: 15 04 10 46 mov a0,a5 1a98: 14 04 31 46 mov a1,a4 1a9c: 00 90 f5 6e hw_ldq/p t9,0(a5) 1aa0: d6 04 55 46 cmovne a2,a5,t8 1aa4: 18 08 d7 46 xor t8,t9,t10 1aa8: 03 00 00 f7 bne t10,0x1ab8 1aac: 34 35 80 42 subq a4,0x1,a4 1ab0: 15 14 a1 42 addq a5,0x8,a5 1ab4: f9 ff 9f fe bgt a4,0x1a9c 1ab8: 01 80 fe 6b ret zero,(sp),0x1 ; stl_checked(t8, a5, t11) ; Write longword to a physical address, read back and compare. ; In case of miscompare, display error code on diagnostic LEDs and halt. ; Inputs: t8 - longword value to write ; a5 - physical address ; t11 - error code 1abc: 00 80 d5 7e hw_stl/p t8,0(a5) 1ac0: 00 40 ff 63 mb 1ac4: 00 80 f5 6e hw_ldl/p t9,0(a5) 1ac8: 17 16 fe 4a zap t9,0xf0,t9 1acc: 18 08 f6 46 xor t9,t8,t10 1ad0: 01 00 00 e7 beq t10,0x1ad8 1ad4: 31 ff bf d3 bsr gp,0x179c ; diag_leds(t11) 1ad8: 01 80 fe 6b ret zero,(sp),0x1 ; stl_with_read_back(t8, a5) ; Write longword to a physical address, read back and compare. ; Inputs: t8 - longword value to write ; a5 - physical address ; Returns: t10 - XOR of the value stored with the read back value. 1adc: 00 80 d5 7e hw_stl/p t8,0(a5) 1ae0: 00 40 ff 63 mb 1ae4: 00 80 f5 6e hw_ldl/p t9,0(a5) 1ae8: 17 16 fe 4a zap t9,0xf0,t9 1aec: 18 08 f6 46 xor t9,t8,t10 1af0: 01 80 fe 6b ret zero,(sp),0x1 ; wait(a0) 1af4: 56 01 00 64 hw_mfpr v0,0x156 ; PALtemp22 1af8: c0 94 00 48 extll v0,0x4,v0 1afc: 01 00 00 f4 bne v0,0x1b04 1b00: 0a 01 1f 20 lda v0,266 1b04: 00 04 10 4c mulq v0,a0,v0 1b08: 01 00 9f 22 lda a4,1 1b0c: 34 17 84 4a sll a4,0x20,a4 1b10: 0e 02 94 76 hw_mtpr a4,0x20e ; CC_CTL 1b14: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 1b18: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 1b1c: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 1b20: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 1b24: 00 c0 9f 62 rpcc a4 1b28: 34 f6 81 4a zapnot a4,0xf,a4 1b2c: b4 09 14 40 cmplt v0,a4,a4 1b30: fc ff 9f e6 beq a4,0x1b24 1b34: 01 80 fe 6b ret zero,(sp),0x1 ; save regs and wait(a0) 1b38: 02 00 00 d0 bsr v0,0x1b44 ; save_regs() 1b3c: ed ff df d3 bsr sp,0x1af4 1b40: 12 00 e0 c3 br 0x1b8c ; restore_regs() ; save_regs() 1b44: 41 01 de 77 hw_mtpr sp,0x141 ; PALtemp1 1b48: 42 01 42 74 hw_mtpr t1,0x142 ; PALtemp2 1b4c: 43 01 63 74 hw_mtpr t2,0x143 ; PALtemp3 1b50: 44 01 84 74 hw_mtpr t3,0x144 ; PALtemp4 1b54: 45 01 a5 74 hw_mtpr t4,0x145 ; PALtemp5 1b58: 46 01 c6 74 hw_mtpr t5,0x146 ; PALtemp6 1b5c: 47 01 e7 74 hw_mtpr t6,0x147 ; PALtemp7 1b60: 48 01 08 75 hw_mtpr t7,0x148 ; PALtemp8 1b64: 49 01 29 75 hw_mtpr s0,0x149 ; PALtemp9 1b68: 4a 01 10 76 hw_mtpr a0,0x14a ; PALtemp10 1b6c: 4b 01 31 76 hw_mtpr a1,0x14b ; PALtemp11 1b70: 4c 01 52 76 hw_mtpr a2,0x14c ; PALtemp12 1b74: 4d 01 73 76 hw_mtpr a3,0x14d ; PALtemp13 1b78: 4e 01 5a 77 hw_mtpr ra,0x14e ; PALtemp14 1b7c: 4f 01 7b 77 hw_mtpr t12,0x14f ; PALtemp15 1b80: 50 01 9c 77 hw_mtpr at,0x150 ; PALtemp16 1b84: 51 01 bd 77 hw_mtpr gp,0x151 ; PALtemp17 1b88: 01 80 e0 6b ret zero,(v0),0x1 ; restore_regs() 1b8c: 41 01 de 67 hw_mfpr sp,0x141 ; PALtemp1 1b90: 42 01 42 64 hw_mfpr t1,0x142 ; PALtemp2 1b94: 43 01 63 64 hw_mfpr t2,0x143 ; PALtemp3 1b98: 44 01 84 64 hw_mfpr t3,0x144 ; PALtemp4 1b9c: 45 01 a5 64 hw_mfpr t4,0x145 ; PALtemp5 1ba0: 46 01 c6 64 hw_mfpr t5,0x146 ; PALtemp6 1ba4: 47 01 e7 64 hw_mfpr t6,0x147 ; PALtemp7 1ba8: 48 01 08 65 hw_mfpr t7,0x148 ; PALtemp8 1bac: 49 01 29 65 hw_mfpr s0,0x149 ; PALtemp9 1bb0: 4a 01 10 66 hw_mfpr a0,0x14a ; PALtemp10 1bb4: 4b 01 31 66 hw_mfpr a1,0x14b ; PALtemp11 1bb8: 4c 01 52 66 hw_mfpr a2,0x14c ; PALtemp12 1bbc: 4d 01 73 66 hw_mfpr a3,0x14d ; PALtemp13 1bc0: 4e 01 5a 67 hw_mfpr ra,0x14e ; PALtemp14 1bc4: 4f 01 7b 67 hw_mfpr t12,0x14f ; PALtemp15 1bc8: 50 01 9c 67 hw_mfpr at,0x150 ; PALtemp16 1bcc: 51 01 bd 67 hw_mfpr gp,0x151 ; PALtemp17 1bd0: 1f 04 ff 47 nop 1bd4: 01 80 fe 6b ret zero,(sp),0x1 1bd8: 1d 00 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 1bdc: 09 00 1f 22 lda a0,9 1be0: 20 00 c0 d3 bsr sp,0x1c64 ; sl_xmit_byte(a0) 1be4: 91 16 44 4a srl a2,0x20,a1 1be8: 0d 00 a0 d3 bsr gp,0x1c20 ; print_hex_longword(a1) 1bec: 2e 00 1f 22 lda a0,46 1bf0: 1c 00 c0 d3 bsr sp,0x1c64 ; sl_xmit_byte(a0) 1bf4: 03 00 e0 c3 br 0x1c04 1bf8: 15 00 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 1bfc: 09 00 1f 22 lda a0,9 1c00: 18 00 c0 d3 bsr sp,0x1c64 ; sl_xmit_byte(a0) 1c04: 31 f6 41 4a zapnot a2,0xf,a1 1c08: 05 00 a0 d3 bsr gp,0x1c20 ; print_hex_longword(a1) 1c0c: 0d 0a 7f 22 lda a3,2573 ; '\r\n' 1c10: 0f 00 a0 d3 bsr gp,0x1c50 ; sl_xmit(a3) 1c14: 01 80 fa 6b ret ; print_hex_byte(a1) ; Print out a byte as two hex digits to the SROM debug port. ; Input: a1 - byte value to print. 1c18: 02 00 1f 20 lda v0,2 1c1c: 01 00 e0 c3 br 0x1c24 ; Entry print_hex_longword(a1) ; Print out a longword as eight hex digits to the SROM debug port. ; Input: a1 - value to print. 1c20: 08 00 1f 20 lda v0,8 1c24: 13 04 ff 47 clr a3 1c28: 33 17 61 4a sll a3,0x8,a3 1c2c: 01 f0 21 46 and a1,0xf,t0 1c30: 01 14 26 40 addq t0,0x30,t0 1c34: a2 59 27 40 cmplt t0,0x3a,t1 1c38: 01 00 40 f4 bne t1,0x1c40 1c3c: 01 f4 24 40 addq t0,0x27,t0 1c40: 13 04 33 44 or t0,a3,a3 1c44: 91 96 20 4a srl a1,0x4,a1 1c48: 20 35 00 40 subq v0,0x1,v0 1c4c: f6 ff 1f f4 bne v0,0x1c28 ; Entry sl_xmit(a3) ; Transmit a string of up to 8 characters to the SROM debug port. ; Input: a3 - NUL terminated string. 1c50: 30 36 60 4a zapnot a3,0x1,a0 1c54: 03 00 c0 d3 bsr sp,0x1c64 ; sl_xmit_byte(a0) 1c58: 93 16 61 4a srl a3,0x8,a3 1c5c: fc ff 7f f6 bne a3,0x1c50 1c60: 01 80 fd 6b ret zero,(gp),0x1 ; sl_xmit_byte(a0) ; Transmit a byte to the SROM debug port. ; Input: a0 - byte to transmit. 1c64: 56 01 00 64 hw_mfpr v0,0x156 ; PALtemp22 1c68: 00 10 10 44 and v0,0x80,v0 1c6c: 0b 00 00 e4 beq v0,0x1c9c 1c70: 14 00 9f 20 lda t3,20 1c74: 00 ff 10 22 lda a0,-256(a0) 1c78: 30 17 01 4a sll a0,0x8,a0 1c7c: 01 00 1f 20 lda v0,1 1c80: 20 37 04 48 sll v0,0x21,v0 1c84: 15 01 00 74 hw_mtpr v0,0x115 ; HWINT_CLR 1c88: 16 01 10 76 hw_mtpr a0,0x116 ; SL_XMIT 1c8c: 90 36 00 4a srl a0,0x1,a0 1c90: 24 35 80 40 subq t3,0x1,t3 1c94: 04 00 60 d3 bsr t12,0x1ca8 1c98: f8 ff 9f f4 bne t3,0x1c7c 1c9c: 01 80 fe 6b ret zero,(sp),0x1 1ca0: 07 34 e0 47 mov 0x1,t6 1ca4: 01 00 e0 c3 br 0x1cac 1ca8: 07 04 ff 47 clr t6 1cac: 56 01 00 64 hw_mfpr v0,0x156 ; PALtemp22 1cb0: c0 94 00 48 extll v0,0x4,v0 1cb4: 00 94 06 4c mulq v0,0x34,v0 1cb8: 80 06 07 48 srl v0,t6,v0 1cbc: 01 00 ff 20 lda t6,1 1cc0: 27 17 e4 48 sll t6,0x20,t6 1cc4: 0e 02 e7 74 hw_mtpr t6,0x20e ; CC_CTL 1cc8: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 1ccc: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 1cd0: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 1cd4: 40 01 ff 67 hw_mfpr zero,0x140 ; PALtemp0 1cd8: 00 c0 ff 60 rpcc t6 1cdc: 27 f6 e1 48 zapnot t6,0xf,t6 1ce0: a7 09 07 40 cmplt v0,t6,t6 1ce4: fc ff ff e4 beq t6,0x1cd8 1ce8: 01 80 fb 6b ret zero,(t12),0x1 ; sl_xmit_byte_nc(a0) ; Transmit a byte to the SROM debug port (no-clobber). ; Save and restore registers around the call to sl_xmit_byte(a0). ; Input: a0 - byte to transmit. 1cec: 95 ff 1f d0 bsr v0,0x1b44 ; save_regs() 1cf0: dc ff df d3 bsr sp,0x1c64 ; sl_xmit_byte(a0) 1cf4: a5 ff ff c3 br 0x1b8c ; restore_regs() ; sl_xmit_nc(a3) ; Transmit a string of up to 8 characters to the SROM debug port (no-clobber). ; Save and restore registers around the call to sl_xmit(a3). ; Input: a3 - NUL terminated string. 1cf8: 92 ff 1f d0 bsr v0,0x1b44 ; save_regs() 1cfc: d4 ff bf d3 bsr gp,0x1c50 ; sl_xmit(a3) 1d00: a2 ff ff c3 br 0x1b8c ; restore_regs() ; print_hex_byte_nc(a1) ; Print out a byte as two hex digits to the SROM debug port (no-clobber). ; Save and restore registers around the call to print_hex_byte(a1). ; Input: a1 - byte value to print. 1d04: 8f ff 1f d0 bsr v0,0x1b44 ; save_regs() 1d08: c3 ff bf d3 bsr gp,0x1c18 ; print_hex_byte(a1) 1d0c: 9f ff ff c3 br 0x1b8c ; restore_regs() ; print_hex_longword_nc(a1) ; Print out a longword as eight hex digits to the SROM debug port (no-clobber). ; Save and restore registers around the call to print_hex_longword(a1). ; Input: a1 - value to print. 1d10: 8c ff 1f d0 bsr v0,0x1b44 ; save_regs() 1d14: c2 ff bf d3 bsr gp,0x1c20 ; print_hex_longword(a1) 1d18: 9c ff ff c3 br 0x1b8c ; restore_regs() ; print_name_and_quadword_nc(a3, a2) ; Inputs: a3 - string to print before the value ; a2 - value to print in hexadecimal 1d1c: 89 ff 1f d0 bsr v0,0x1b44 ; save_regs() 1d20: ad ff 5f d3 bsr ra,0x1bd8 1d24: 99 ff ff c3 br 0x1b8c ; restore_regs() ; print_name_and_longword_nc(a3, a2) ; Inputs: a3 - string to print before the value ; a2 - value to print in hexadecimal 1d28: 86 ff 1f d0 bsr v0,0x1b44 ; save_regs() 1d2c: b2 ff 5f d3 bsr ra,0x1bf8 1d30: 96 ff ff c3 br 0x1b8c ; restore_regs() ; Entry points into PCI I/O space reads of various sizes. ; Input: a0 - PCI I/O address. ; v0 = pci_io_read_byte(a0) 1d34: 08 00 ff 21 lda fp,8 1d38: 05 00 e0 c3 br 0x1d50 ; v0 = pci_io_read_word(a0) 1d3c: 09 00 ff 21 lda fp,9 1d40: 03 00 e0 c3 br 0x1d50 ; v0 = pci_io_read_tribyte(a0) - does anyone ever use this? 1d44: 0a 00 ff 21 lda fp,10 1d48: 01 00 e0 c3 br 0x1d50 ; v0 = pci_io_read_longword(a0) 1d4c: 0b 00 ff 21 lda fp,11 ; v0 = pci_read(fp, a0) ; Inputs: fp - PCI space type and width of access ; a0 - address in the PCI space selected by fp 1d50: 16 00 c0 d3 bsr sp,0x1dac ; t11 = pci_addr(fp, a0) 1d54: 00 80 01 6c hw_ldl/p v0,0(t0) 1d58: 19 70 00 46 and a0,0x3,t11 ; two last bits of the PCI address 1d5c: 39 77 20 4b sll t11,0x3,t11 1d60: 80 06 19 48 srl v0,t11,v0 ; shift byte lanes of the value 1d64: 19 70 e0 45 and fp,0x3,t11 1d68: 19 34 20 43 addq t11,0x1,t11 1d6c: 40 06 19 48 mskql v0,t11,v0 ; mask bytes according to request width 1d70: 01 80 fd 6b ret zero,(gp),0x1 ; Entry points into PCI I/O space writes of various sizes. ; Inputs: a0 - PCI I/O address ; a1 - value to write ; pci_io_write_byte(a0, a1) 1d74: 08 00 ff 21 lda fp,8 1d78: 05 00 e0 c3 br 0x1d90 ; pci_io_write_word(a0, a1) 1d7c: 09 00 ff 21 lda fp,9 1d80: 03 00 e0 c3 br 0x1d90 ; pci_io_write_tribyte(a0, a1) 1d84: 0a 00 ff 21 lda fp,10 1d88: 01 00 e0 c3 br 0x1d90 ; pci_io_write_longword(a0, a1) 1d8c: 0b 00 ff 21 lda fp,11 ; pci_write(fp, a0, a1) ; Inputs: fp - PCI space type and width of access ; a0 - address in the PCI space selected by fp ; a1 - value to write to PCI bus at address a0 1d90: 06 00 c0 d3 bsr sp,0x1dac ; t11 = pci_addr(fp, a0) 1d94: 00 70 00 46 and a0,0x3,v0 1d98: 20 77 00 48 sll v0,0x3,v0 1d9c: 20 07 20 4a sll a1,v0,v0 ; shift into correct byte lanes 1da0: 00 80 01 7c hw_stl/p v0,0(t0) 1da4: 00 40 ff 63 mb 1da8: 01 80 fd 6b ret zero,(gp),0x1 ; t11 = pci_addr(fp, a0) ; PCI space address calculation routine. ; 85.8000.0000 - PCI I/O sparse space - 64 MB: ; fp = 8: t11 = 85.8000.0000 + (a0 << 5) - byte at a0 ; fp = 9: t11 = 85.8000.0008 + (a0 << 5) - word at a0 ; fp = 10: t11 = 85.8000.0010 + (a0 << 5) - tribyte at a0 ; fp = 11: t11 = 85.8000.0018 + (a0 << 5) - longword at a0 ; 87.0000.0000 - PCI configuration sparse space: ; fp = 0xYY000c: t11 = 87.00YY.0000 + (a0 << 5) - byte reg. a0 1dac: 58 08 3f 23 lda t11,2136 1db0: 70 08 39 27 ldah t11,2160(t11) 1db4: 39 17 24 4b sll t11,0x20,t11 1db8: 60 08 39 23 lda t11,2144(t11) 1dbc: 00 08 39 27 ldah t11,2048(t11) ; 0870.0858.0800.0860 1dc0: 80 56 e0 49 srl fp,0x2,v0 1dc4: 00 70 00 44 and v0,0x3,v0 ; v0 = fp<3:2> 1dc8: 21 37 00 48 sll v0,0x1,t0 1dcc: c1 02 21 4b extwl t11,t0,t0 1dd0: 21 97 23 48 sll t0,0x1c,t0 ; t0 = basereg[fp<3:2>] 1dd4: b9 15 00 40 cmpeq v0,0,t11 1dd8: 17 00 20 f7 bne t11,0x1e38 ; br if [0] - 86.0000.0000 - PCI memory, dense space 1ddc: a0 75 00 40 cmpeq v0,0x3,v0 1de0: 0f 00 00 e4 beq v0,0x1e20 ; br if [1/2] - 8x.x000.0000 1de4: 80 96 e0 49 srl fp,0x4,v0 ; here if [3] - 87.0000.0000 - PCI config. space (sparse) 1de8: 00 70 00 44 and v0,0x3,v0 ; v0 = fp<5:4> 1dec: 74 08 3f 23 lda t11,2164 ; 0x874 1df0: 39 97 23 4b sll t11,0x1c,t11 1df4: 80 04 39 23 lda t11,1152(t11) ; 87.4000.0480 - CIA CFG register (PCI config. type) 1df8: 00 80 19 7c hw_stl/p v0,0(t11) ; write fp<5:4> - 0 direct, 1 behind PCI-PCI bridge 1dfc: 99 16 e2 49 srl fp,0x10,t11 1e00: 19 f0 3f 47 and t11,0xff,t11 1e04: 39 17 22 4b sll t11,0x10,t11 ; t11 = fp<23:16> << 16 - device for IDSEL 1e08: 01 04 21 47 or t11,t0,t0 1e0c: 04 00 00 e4 beq v0,0x1e20 1e10: 99 16 e1 49 srl fp,0x8,t11 1e14: 19 f0 3f 47 and t11,0xff,t11 1e18: 39 b7 22 4b sll t11,0x15,t11 1e1c: 01 04 21 47 or t11,t0,t0 1e20: 39 b7 00 4a sll a0,0x5,t11 1e24: 01 04 21 47 or t11,t0,t0 1e28: 80 16 e0 49 srl fp,0,v0 1e2c: 00 70 e0 45 and fp,0x3,v0 1e30: 20 77 00 48 sll v0,0x3,v0 1e34: 01 04 20 44 or t0,v0,t0 1e38: 01 80 fe 6b ret zero,(sp),0x1 ; Intel 82375 PCEB PCI-to-EISA bridge configuration 1e3c: 0c 00 ff 21 lda fp,12 1e40: 0f 96 e0 49 zap fp,0x4,fp 1e44: 0a 00 1f 24 ldah v0,10 1e48: 0f 04 0f 44 or v0,fp,fp ; fp = 0xa000c: Intel PCEB conf. space, byte access 1e4c: 0d 00 1f 22 lda a0,13 1e50: f8 00 3f 22 lda a1,248 1e54: ce ff bf d3 bsr gp,0x1d90 ; PCEB conf. 0D MLTIM <- 0xF8 1e58: 40 00 1f 22 lda a0,64 1e5c: 68 00 3f 22 lda a1,104 1e60: cb ff bf d3 bsr gp,0x1d90 ; PCEB conf. 40 PCICON <- 0x68 1e64: 41 00 1f 22 lda a0,65 1e68: 8d 00 3f 22 lda a1,141 1e6c: c8 ff bf d3 bsr gp,0x1d90 ; ARBCON 1e70: 42 00 1f 22 lda a0,66 1e74: f0 00 3f 22 lda a1,240 1e78: c5 ff bf d3 bsr gp,0x1d90 ; ARBPRI 1e7c: 44 00 1f 22 lda a0,68 1e80: 10 00 3f 22 lda a1,16 1e84: c2 ff bf d3 bsr gp,0x1d90 ; MCSCON 1e88: 0f 00 ff 21 lda fp,15 1e8c: 0f 96 e0 49 zap fp,0x4,fp 1e90: 0a 00 1f 24 ldah v0,10 1e94: 0f 04 0f 44 or v0,fp,fp ; fp = 0xa000f: longword access 1e98: 60 00 1f 22 lda a0,96 1e9c: ff ff 3f 26 ldah a1,-1 1ea0: 31 f6 21 4a zapnot a1,0xf,a1 1ea4: ba ff bf d3 bsr gp,0x1d90 ; MEMREGN 1ea8: 70 00 1f 22 lda a0,112 1eac: b8 ff bf d3 bsr gp,0x1d90 ; IOREGN 1eb0: 01 80 fb 6b ret zero,(t12),0x1 ; Configure EISA ports 0x22, 0x398-0x399, and 0x3f8-0x3fb. ; These are system board devices. 1eb4: 09 00 ff 21 lda fp,9 ; PCI I/O space, word (16-bit) access 1eb8: 22 00 1f 22 lda a0,34 ; 0x22 1ebc: 02 0f 3f 22 lda a1,3842 ; 0x0f02 1ec0: b3 ff bf d3 bsr gp,0x1d90 ; EISA port 0x22 <- 0x0f02 1ec4: 22 00 1f 22 lda a0,34 1ec8: 40 67 3f 22 lda a1,26432 ; 0x6740 1ecc: b0 ff bf d3 bsr gp,0x1d90 ; EISA port 0x22 <- 0x6740 1ed0: 22 00 1f 22 lda a0,34 1ed4: 4e 03 3f 22 lda a1,846 ; 0x34e 1ed8: ad ff bf d3 bsr gp,0x1d90 ; EISA port 0x22 <- 0x034e 1edc: 22 00 1f 22 lda a0,34 1ee0: 4f ff 3f 22 lda a1,-177 ; 0xff4f 1ee4: 01 00 31 26 ldah a1,1(a1) 1ee8: a9 ff bf d3 bsr gp,0x1d90 ; EISA port 0x22 <- 0xff4f 1eec: 08 00 ff 21 lda fp,8 ; PCI I/O space, byte access 1ef0: fb 03 1f 22 lda a0,1019 ; 0x3fb 1ef4: 80 00 3f 22 lda a1,128 ; 0x80 1ef8: a5 ff bf d3 bsr gp,0x1d90 ; EISA port 0x3fb <- 0x80 1efc: f8 03 1f 22 lda a0,1016 ; 0x3f8 1f00: 0c 00 3f 22 lda a1,12 ; 0xc 1f04: a2 ff bf d3 bsr gp,0x1d90 ; EISA port 0x3f8 <- 0x0c 1f08: f9 03 1f 22 lda a0,1017 ; 0x3f9 1f0c: 00 00 3f 22 lda a1,0 1f10: 9f ff bf d3 bsr gp,0x1d90 ; EISA port 0x3f9 <- 0x00 1f14: fb 03 1f 22 lda a0,1019 ; 0x3fb 1f18: 03 00 3f 22 lda a1,3 1f1c: 9c ff bf d3 bsr gp,0x1d90 ; EISA port 0x3fb <- 0x03 1f20: fa 03 1f 22 lda a0,1018 ; 0x3fa 1f24: 07 00 3f 22 lda a1,7 1f28: 99 ff bf d3 bsr gp,0x1d90 ; EISA port 0x3fa <- 0x07 1f2c: 98 03 1f 22 lda a0,920 ; 0x398 1f30: 87 ff bf d3 bsr gp,0x1d50 ; v0 <- EISA port 0x398 (byte) 1f34: 98 03 1f 22 lda a0,920 1f38: 85 ff bf d3 bsr gp,0x1d50 ; and same again 1f3c: 98 03 1f 22 lda a0,920 1f40: 00 00 3f 22 lda a1,0 1f44: 92 ff bf d3 bsr gp,0x1d90 ; EISA port 0x398 <- 0x00 1f48: 99 03 1f 22 lda a0,921 ; 0x399 1f4c: 0f 00 3f 22 lda a1,15 1f50: 8f ff bf d3 bsr gp,0x1d90 ; EISA port 0x399 <- 0x0f 1f54: 99 03 1f 22 lda a0,921 1f58: 0f 00 3f 22 lda a1,15 1f5c: 8c ff bf d3 bsr gp,0x1d90 ; EISA port 0x399 <- 0x0f (again) 1f60: 01 80 fb 6b ret zero,(t12),0x1 ...